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d a t a sh eet objective speci?cation supersedes data of 1996 jul 26 file under integrated circuits, ic22 1996 sep 04 integrated circuits SAA7140A; saa7140b high performance scaler (hps)
1996 sep 04 2 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b contents 1 features 2 general description 3 ordering information 4 block diagram 5 pinning (SAA7140A) 6 pinning (saa7140b) 7 functional description 7.1 data format/reformatter and reference signal generation 7.1.1 data formats and reference signals of the dmsd port 7.1.2 data formats and reference signals of the expansion port 7.2 acquisition control 7.3 bcs control 7.4 scaling unit 7.4.1 horizontal prescaling 7.4.2 vertical scaler 7.4.3 horizontal variable phase scaling 7.5 csm (colour space matrix), dither and gamma correction 7.6 output formatter and output fifo register 7.6.1 data formats and reference signals of the vram port 7.7 data transfer modes 7.7.1 expansion port modes 7.8 vram port modes 7.8.1 data burst transfer mode (fifo mode) 7.8.2 continuous data transfer mode (transparent mode) 7.8.3 i 2 c-bus controlled pseudo sleep mode 8i 2 c-bus protocol 8.1 i 2 c-bus format 8.2 i 2 c-bus bitmap 8.3 description of the i 2 c-bus bits 8.3.1 initial settings for the expansion and dmsd port; subaddress 00h 8.3.2 initial settings for the vram port; subaddress 01h 8.3.3 port i/o control; subaddress 21h 8.3.4 register set a (02h to 1fh) and b (22h to 3fh) 9 limiting values 10 handling 11 thermal characteristics 12 dc characteristics 13 ac characteristics 14 package outline 15 soldering 15.1 introduction 15.2 reflow soldering 15.3 wave soldering 15.3.1 qfp 15.3.2 so 15.3.3 method (qfp and so) 15.4 repairing soldered joints 16 definitions 17 life support applications 18 purchase of philips i 2 c components
1996 sep 04 3 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 1 features scaling of video pictures down to randomly sized windows horizontal upscaling (zoom) two dimensional phase-correct data processing for improved signal quality of scaled data, especially for compression applications processing of a maximum of 2047 active samples per line (v-processing in bypass) and 2047 active lines per frame 16-bit yuv data input port bidirectional expansion port with full duplex functionality (d1) or 16-bit yuv input/output discontinuous data stream supported field-wise switching between two data sources two independent i 2 c-bus programming sets brightness, contrast and saturation controls for scaled outputs chroma key ( a generation) yuv-to-rgb conversion including anti-gamma correction for rgb 16-word fifo register for 32-bit output data output configurable for 32, 24, 16 and 8-bit video data scaled 16-bit 4 :2:2 yuv output scaled 15-bit rgb (5, 5, 5) + a with dither and 24-bit rgb (8, 8, 8) + a output scaled 8-bit monochrome output four independent user configurable general purpose i/o pins low power consumption in i 2 c-bus controlled pseudo sleep mode support of 5 v (SAA7140A) and pure 3.3 v (saa7140b) signalling environment . 2 general description the SAA7140A and saa7140b are cmos high performance scaler (hps) and is a highly integrated circuit designed for use in desktop video (dtv) applications. the devices resample digital video signals using two dimensional phase-correct interpolation in order to display it in an arbitrarily sized window. the SAA7140A fits perfectly into a 5 v signal environment and requires two different supply voltages (5 v and 3.3 v). the saa7140b is a pure 3.3 v design and therefore has only 3.3 v supply pins. with respect to functions and programming, both devices are identical. the devices incorporate additional functions such as control of brightness, saturation, contrast, chroma key generation, yuv-to-rgb conversion, compensation of gamma precorrection, dithering and choice of several output formats. the SAA7140A and saa7140b accepts data from 1 or 2 input signal sources, via its 16-bit yuv input port and/or the bidirectional expansion port. they deliver scaled data on the 32-bit vro output port and, if selected, also on the bidirectional expansion port. a synchronous (transparent) together with an asynchronous (burst) data transfer mode is supported at the 32-bit vro port. 3 ordering information type number package name description version SAA7140A lqfp128 plastic low pro?le quad ?at package; 128 leads; body 14 20 1.4 mm sot425-1 saa7140b lqfp128 plastic low pro?le quad ?at package; 128 leads; body 14 20 1.4 mm sot425-1
1996 sep 04 4 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 4 block diagrams n dbook, full pagewidth expansion port interface data formatter/ reformatter and reference signal generation acquisition control bcs control csm dithering g -correction output formatter output fifo register horizontal prescaling horizontal fine scaling y uv h pxq v y uv y u v vertical processing scaling unit control i 2 c control controls status vro31 to 0 57 to 65, 70 to 81, 86 to 96 47 hgtv vsyv fldv 46 45 48 55 54 pxqv incadr hfl vclk voen v ddd(core) 1 to 4 v ssd(core) 1 to 4 v ddd(bord) 1 to 12 v ssd(bord) 1 to 11 llcin pxqin hin vin vidh7 to 0 vidl7 to 0 llcio pxqio hio vio fdio reference yin7 to 0 uvin7 to 0 cref href vs llc clk scl port3 to 0 sda iicsa res y u v r g b 1 125 126 127 105 to 112 117 to 124 128 104 103 102 97 18 to 11 28 to 21 6 7 8 32 31 33 42 52 43 44 49 50 56 38 to 41 5 vmux ap sp btst y u v line memory arithmetic expansion port SAA7140A vram port dmsd port mha117 fig.1 block diagram (SAA7140A).
1996 sep 04 5 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b h andbook, full pagewidth expansion port interface data formatter/ reformatter and reference signal generation acquisition control bcs control csm dithering g -correction output formatter output fifo register horizontal prescaling horizontal fine scaling y uv h pxq v y uv y u v vertical processing scaling unit control i 2 c control controls status vro31 to 0 57 to 65, 70 to 81, 86 to 96 47 hgtv vsyv fldv 46 45 48 55 54 pxqv incadr hfl vclk voen v ddd1 to 16 v ssd1 to 15 llcin pxqin hin vin vidh7 to 0 vidl7 to 0 llcio pxqio hio vio fdio reference yin7 to 0 uvin7 to 0 cref href vs llc clk scl port3 to 0 sda iicsa res y u v r g b 1 125 126 127 105 to 112 117 to 124 128 104 103 102 97 18 to 11 28 to 21 6 7 8 32 31 33 42 52 43 44 49 50 56 38 to 41 5 vmux ap sp btst y u v line memory arithmetic expansion port saa7140b vram port dmsd port mha360 fig.2 block diagram (saa7140b).
1996 sep 04 6 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 5 pinning (SAA7140A) symbol pin i/o description llcin 1 i line-locked system clock input; expansion port v ddd(bord)1 2 - digital border supply voltage 1 (+5 v) v ssd(bord)1 3 - digital border ground 1 (0 v) v ddd(bord)2 4 - digital border supply voltage 2 (+5 v) llc 5 i line-locked system clock input, maximum 32 mhz (2 pixel rate); dmsd port cref 6 i clock quali?er input (high indicates valid input data yuv on dmsd port) href 7 i horizontal reference input signal; dmsd port vs 8 i vertical sync input signal; dmsd port v ddd(core)1 9 - digital core supply voltage 1 (+3.3 v) v ssd(bord)2 10 - digital border ground 2 (0 v) yin0 11 i luminance input data (bit 0); dmsd port yin1 12 i luminance input data (bit 1); dmsd port yin2 13 i luminance input data (bit 2); dmsd port yin3 14 i luminance input data (bit 3); dmsd port yin4 15 i luminance input data (bit 4); dmsd port yin5 16 i luminance input data (bit 5); dmsd port yin6 17 i luminance input data (bit 6); dmsd port yin7 18 i luminance input data (bit 7); dmsd port v ddd(bord)3 19 - digital border supply voltage 3 (+5 v) v ssd(core)1 20 - digital core ground 1 (0 v) uvin0 21 i time-multiplexed colour-difference input data (bit 0); dmsd port uvin1 22 i time-multiplexed colour-difference input data (bit 1); dmsd port uvin2 23 i time-multiplexed colour-difference input data (bit 2); dmsd port uvin3 24 i time-multiplexed colour-difference input data (bit 3); dmsd port uvin4 25 i time-multiplexed colour-difference input data (bit 4); dmsd port uvin5 26 i time-multiplexed colour-difference input data (bit 5); dmsd port uvin6 27 i time-multiplexed colour-difference input data (bit 6); dmsd port uvin7 28 i time-multiplexed colour-difference input data (bit 7); dmsd port v ddd(bord)4 29 - digital border supply voltage 4 (+5 v) v ssd(bord)3 30 - digital border ground 3 (0 v) sda 31 i/o serial data input/output (i 2 c-bus) scl 32 i serial clock input (i 2 c-bus) iicsa 33 i set address input (i 2 c-bus) v ddd(bord)5 34 - digital border supply voltage 5 (+5 v) v ssd(bord)4 35 - digital border ground 4 (0 v) v ddd(bord)6 36 - digital border supply voltage 6 (+5 v) v ssd(bord)5 37 - digital border ground 5 (0 v) port3 38 i/o general purpose port 3 input/output (set via i 2 c-bus) port2 39 i/o general purpose port 2 input/output (set via i 2 c-bus) port1 40 i/o general purpose port 1 input/output (set via i 2 c-bus)
1996 sep 04 7 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b port0 41 i/o general purpose port 0 input/output (set via i 2 c-bus) res 42 i reset input (active low for at least 30 clock cycles) ap 43 i connected to ground (action pin for testing) sp 44 i connected to ground (shift pin for testing) fldv 45 o ?eld identi?cation output signal; vram port vsyv 46 o vertical sync output signal; vram port hgtv 47 o horizontal reference output signal; vram port pxqv 48 o pixel quali?er output signal to mark active pixels of a quali?ed line; vram port btst 49 i connected to ground; btst = high sets all outputs to high-impedance state (testing) voen 50 i enable input signal for vram port v ddd(core)2 51 - digital core supply voltage 2 (+3.3 v) vmux 52 i vram output multiplexing, control input for the 32 to 16-bit multiplexer v ssd(core)2 53 - digital core ground 2 (0 v) hfl 54 o fifo half-full ?ag output signal incadr 55 o line increment/vertical reset control output vclk 56 i/o clock input/output signal for vram port vro31 57 o 32-bit digital vram port output (bit 31) vro30 58 o 32-bit digital vram port output (bit 30) vro29 59 o 32-bit digital vram port output (bit 29) vro28 60 o 32-bit digital vram port output (bit 28) vro27 61 o 32-bit digital vram port output (bit 27) vro26 62 o 32-bit digital vram port output (bit 26) vro25 63 o 32-bit digital vram port output (bit 25) vro24 64 o 32-bit digital vram port output (bit 24) vro23 65 o 32-bit digital vram port output (bit 23) v ddd(bord)7 66 - digital border supply voltage 7 (+5 v) v ssd(bord)6 67 - digital border ground 6 (0 v) v ddd(bord)8 68 - digital border supply voltage 8 (+5 v) v ssd(bord)7 69 - digital border ground 7 (0 v) vro22 70 o 32-bit vram port output (bit 22) vro21 71 o 32-bit vram port output (bit 21) vro20 72 o 32-bit vram port output (bit 20) vro19 73 o 32-bit vram port output (bit 19) vro18 74 o 32-bit vram port output (bit 18) vro17 75 o 32-bit vram port output (bit 17) vro16 76 o 32-bit vram port output (bit 16) vro15 77 o 32-bit vram port output (bit 15) vro14 78 o 32-bit vram port output (bit 14) vro13 79 o 32-bit vram port output (bit 13) vro12 80 o 32-bit vram port output (bit 12) symbol pin i/o description
1996 sep 04 8 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b vro11 81 o 32-bit vram port output (bit 11) v ssd(bord)8 82 - digital border ground 8 (0 v) v ddd(bord)9 83 - digital border supply voltage 9 (+5 v) v ssd(core)3 84 - digital core ground 3 (0 v) v ddd(core)3 85 - digital core supply voltage 3 (+3.3 v) vro10 86 o 32-bit vram port output (bit 10) vro9 87 o 32-bit vram port output (bit 9) vro8 88 o 32-bit vram port output (bit 8) vro7 89 o 32-bit vram port output (bit 7) vro6 90 o 32-bit vram port output (bit 6) vro5 91 o 32-bit vram port output (bit 5) vro4 92 o 32-bit vram port output (bit 4) vro3 93 o 32-bit vram port output (bit 3) vro2 94 o 32-bit vram port output (bit 2) vro1 95 o 32-bit vram port output (bit 1) vro0 96 o 32-bit vram port output (bit 0) fdio 97 i/o ?eld identi?cation output signal; 7196 dir input signal expansion port, i 2 c-bus controlled v ddd(bord)10 98 - digital border supply voltage 10 (+5 v) v ssd(bord)9 99 - digital border ground 9 (0 v) v ddd(bord)11 100 - digital border supply voltage 11 (+5 v) v ssd(bord)10 101 - digital border ground 10 (0 v) vio 102 i/o vertical sync input/output signal; expansion port hio 103 i/o horizontal sync input/output signal; expansion port pxqio 104 i/o pixel quali?er input/output signal to mark valid pixels; expansion port vidh7 105 i/o bidirectional expansion port, high byte (bit 7) in 16-bit mode luminance component y vidh6 106 i/o bidirectional expansion port, high byte (bit 6) in 16-bit mode luminance component y vidh5 107 i/o bidirectional expansion port, high byte (bit 5) in 16-bit mode luminance component y vidh4 108 i/o bidirectional expansion port, high byte (bit 4) in 16-bit mode luminance component y vidh3 109 i/o bidirectional expansion port, high byte (bit 3) in 16-bit mode luminance component y vidh2 110 i/o bidirectional expansion port, high byte (bit 2) in 16-bit mode luminance component y vidh1 111 i/o bidirectional expansion port, high byte (bit 1) in 16-bit mode luminance component y vidh0 112 i/o bidirectional expansion port, high byte (bit 0) in 16-bit mode luminance component y v ddd(bord)12 113 - digital border supply voltage 12 (+5 v) symbol pin i/o description
1996 sep 04 9 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b v ssd(bord)11 114 - digital border ground 11 (0 v) v ddd(core)4 115 - digital core supply voltage 4 (+3.3 v) v ssd(core)4 116 - digital core ground 4 (0 v) vidl7 117 i/o bidirectional expansion port, low byte (bit 7) in 16-bit mode time-multiplexed colour-difference components u and v vidl6 118 i/o bidirectional expansion port, low byte (bit 6) in 16-bit mode time-multiplexed colour-difference components u and v vidl5 119 i/o bidirectional expansion port, low byte (bit 5) in 16-bit mode time-multiplexed colour-difference components u and v vidl4 120 i/o bidirectional expansion port, low byte (bit 4) in 16-bit mode time-multiplexed colour-difference components u and v vidl3 121 i/o bidirectional expansion port, low byte (bit 3) in 16-bit mode time-multiplexed colour-difference components u and v vidl2 122 i/o bidirectional expansion port, low byte (bit 2) in 16-bit mode time-multiplexed colour-difference components u and v vidl1 123 i/o bidirectional expansion port, low byte (bit 1) in 16-bit mode time-multiplexed colour-difference components u and v vidl0 124 i/o bidirectional expansion port, low byte (bit 0) in 16-bit mode time-multiplexed colour-difference components u and v pxqin 125 i pixel quali?er input signal to mark valid pixels; expansion port hin 126 i horizontal sync input signal; expansion port vin 127 i vertical sync input signal; expansion port llcio 128 i/o line-locked system clock input/output; expansion port symbol pin i/o description
1996 sep 04 10 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b fig.3 pin configuration (SAA7140A). handbook, full pagewidth mha362 SAA7140A 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 101 102 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 v ssd(bord)10 vio v ddd(bord)11 v ssd(bord)9 v ddd(bord)10 fdio vro0 vro1 vro2 vro3 vro4 vro5 vro5 vro7 vro8 vro9 vro10 v ddd(core)3 v ssd(core)3 v ddd(bord)9 v ssd(bord)8 vro11 vro12 vro13 vro14 vro15 vro16 vro17 vro18 vro19 vro20 vro21 vro22 v ssd(bord)7 v ddd(bord)8 v ssd(bord)6 v ddd(bord)7 vro23 v ddd(bord) 1 llcin v ssd(bord)1 v ddd(bord)2 lcc cref href vs v ddd(core)1 v ssd(bord)2 yin0 yin1 yin2 yin3 yin4 yin5 yin6 yin7 v ddd(bord)3 v ssd(core)1 uvin0 uvin1 uvin2 uvin3 uvin4 uvin5 uvin6 uvin7 v ddd(bord)4 v ssd(bord)3 sda scl iicsa v ddd(bord)5 v ssd(bord)4 v ddd(bord)6 v ssd(bord)5 port3 40 39 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 127 128 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 vin llcio hin pxqin vidl0 vidl1 vidl2 vidl3 vidl4 vidl5 vidl6 vidl7 v ssd(core)4 v ddd(core)4 v ssd(bord)11 v ddd(bord)12 vidh0 vidh1 vidh2 vidh3 vidh4 vidh5 vidh6 vidh7 pxqio hio port1 port2 port0 res ap sp fldv vsyv hgtv pxqv btst voen v ddd(core)2 vmux v ssd(core)2 hfl incadr vclk vro31 vro30 vro29 vro28 vro27 vro26 vro25 vro24
1996 sep 04 11 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 6 pinning (saa7140b) symbol pin i/o description llcin 1 i line-locked system clock input; expansion port v ddd1 2 - digital supply voltage 1 (+3.3 v) v ssd1 3 - digital ground 1 (0 v) v ddd2 4 - digital supply voltage 2 (+3.3 v) llc 5 i line-locked system clock input, maximum 32 mhz (2 pixel rate); dmsd port cref 6 i clock quali?er input (high indicates valid input data yuv on dmsd port) href 7 i horizontal reference input signal; dmsd port vs 8 i vertical sync input signal; dmsd port v ddd3 9 - digital supply voltage 3 (+3.3 v) v ssd2 10 - digital ground 2 (0 v) yin0 11 i luminance input data (bit 0); dmsd port yin1 12 i luminance input data (bit 1); dmsd port yin2 13 i luminance input data (bit 2); dmsd port yin3 14 i luminance input data (bit 3); dmsd port yin4 15 i luminance input data (bit 4); dmsd port yin5 16 i luminance input data (bit 5); dmsd port yin6 17 i luminance input data (bit 6); dmsd port yin7 18 i luminance input data (bit 7); dmsd port v ddd4 19 - digital supply voltage 4 (+3.3 v) v ssd3 20 - digital ground 3 (0 v) uvin0 21 i time-multiplexed colour-difference input data (bit 0); dmsd port uvin1 22 i time-multiplexed colour-difference input data (bit 1); dmsd port uvin2 23 i time-multiplexed colour-difference input data (bit 2); dmsd port uvin3 24 i time-multiplexed colour-difference input data (bit 3); dmsd port uvin4 25 i time-multiplexed colour-difference input data (bit 4); dmsd port uvin5 26 i time-multiplexed colour-difference input data (bit 5); dmsd port uvin6 27 i time-multiplexed colour-difference input data (bit 6); dmsd port uvin7 28 i time-multiplexed colour-difference input data (bit 7); dmsd port v ddd5 29 - digital supply voltage 5 (+3.3 v) v ssd4 30 - digital ground 4 (0 v) sda 31 i/o serial data input/output (i 2 c-bus) scl 32 i serial clock input (i 2 c-bus) iicsa 33 i set address input (i 2 c-bus) v ddd6 34 - digital supply voltage 6 (+3.3 v) v ssd5 35 - digital ground 5 (0 v) v ddd7 36 - digital supply voltage 7 (+3.3 v) v ssd6 37 - digital ground 6 (0 v) port3 38 i/o general purpose port 3 input/output (set via i 2 c-bus) port2 39 i/o general purpose port 2 input/output (set via i 2 c-bus) port1 40 i/o general purpose port 1 input/output (set via i 2 c-bus)
1996 sep 04 12 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b port0 41 i/o general purpose port 0 input/output (set via i 2 c-bus) res 42 i reset input (active low for at least 30 clock cycles) ap 43 i connected to ground (action pin for testing) sp 44 i connected to ground (shift pin for testing) fldv 45 o ?eld identi?cation output signal; vram port vsyv 46 o vertical sync output signal; vram port hgtv 47 o horizontal reference output signal; vram port pxqv 48 o pixel quali?er output signal to mark active pixels of a quali?ed line; vram port btst 49 i connected to ground; btst = high sets all outputs to high-impedance state (testing) voen 50 i enable input signal for vram port v ddd8 51 - digital supply voltage 8 (+3.3 v) vmux 52 i vram output multiplexing, control input for the 32 to 16-bit multiplexer v ssd7 53 - digital ground 7 (0 v) hfl 54 o fifo half-full ?ag output signal incadr 55 o line increment/vertical reset control output vclk 56 i/o clock input/output signal for vram port vro31 57 o 32-bit digital vram port output (bit 31) vro30 58 o 32-bit digital vram port output (bit 30) vro29 59 o 32-bit digital vram port output (bit 29) vro28 60 o 32-bit digital vram port output (bit 28) vro27 61 o 32-bit digital vram port output (bit 27) vro26 62 o 32-bit digital vram port output (bit 26) vro25 63 o 32-bit digital vram port output (bit 25) vro24 64 o 32-bit digital vram port output (bit 24) vro23 65 o 32-bit digital vram port output (bit 23) v ddd9 66 - digital supply voltage 9 (+3.3 v) v ssd8 67 - digital ground 8 (0 v) v ddd10 68 - digital supply voltage 10 (+3.3 v) v ssd9 69 - digital ground 9 (0 v) vro22 70 o 32-bit vram port output (bit 22) vro21 71 o 32-bit vram port output (bit 21) vro20 72 o 32-bit vram port output (bit 20) vro19 73 o 32-bit vram port output (bit 19) vro18 74 o 32-bit vram port output (bit 18) vro17 75 o 32-bit vram port output (bit 17) vro16 76 o 32-bit vram port output (bit 16) vro15 77 o 32-bit vram port output (bit 15) vro14 78 o 32-bit vram port output (bit 14) vro13 79 o 32-bit vram port output (bit 13) vro12 80 o 32-bit vram port output (bit 12) symbol pin i/o description
1996 sep 04 13 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b vro11 81 o 32-bit vram port output (bit 11) v ssd10 82 - digital ground 10 (0 v) v ddd11 83 - digital supply voltage 11 (+3.3 v) v ssd11 84 - digital ground 11 (0 v) v ddd12 85 - digital supply voltage 12 (+3.3 v) vro10 86 o 32-bit vram port output (bit 10) vro9 87 o 32-bit vram port output (bit 9) vro8 88 o 32-bit vram port output (bit 8) vro7 89 o 32-bit vram port output (bit 7) vro6 90 o 32-bit vram port output (bit 6) vro5 91 o 32-bit vram port output (bit 5) vro4 92 o 32-bit vram port output (bit 4) vro3 93 o 32-bit vram port output (bit 3) vro2 94 o 32-bit vram port output (bit 2) vro1 95 o 32-bit vram port output (bit 1) vro0 96 o 32-bit vram port output (bit 0) fdio 97 i/o ?eld identi?cation output signal; 7196 dir input signal expansion port, i 2 c-bus controlled v ddd13 98 - digital supply voltage 13 (+3.3 v) v ssd12 99 - digital ground 12 (0 v) v ddd14 100 - digital supply voltage 14 (+3.3 v) v ssd13 101 - digital ground 13 (0 v) vio 102 i/o vertical sync input/output signal; expansion port hio 103 i/o horizontal sync input/output signal; expansion port pxqio 104 i/o pixel quali?er input/output signal to mark valid pixels; expansion port vidh7 105 i/o bidirectional expansion port, high byte (bit 7) in 16-bit mode luminance component y vidh6 106 i/o bidirectional expansion port, high byte (bit 6) in 16-bit mode luminance component y vidh5 107 i/o bidirectional expansion port, high byte (bit 5) in 16-bit mode luminance component y vidh4 108 i/o bidirectional expansion port, high byte (bit 4) in 16-bit mode luminance component y vidh3 109 i/o bidirectional expansion port, high byte (bit 3) in 16-bit mode luminance component y vidh2 110 i/o bidirectional expansion port, high byte (bit 2) in 16-bit mode luminance component y vidh1 111 i/o bidirectional expansion port, high byte (bit 1) in 16-bit mode luminance component y vidh0 112 i/o bidirectional expansion port, high byte (bit 0) in 16-bit mode luminance component y v ddd15 113 - digital supply voltage 15 (+3.3 v) symbol pin i/o description
1996 sep 04 14 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b v ssd14 114 - digital ground 14 (0 v) v ddd16 115 - digital supply voltage 16 (+3.3 v) v ssd15 116 - digital ground 15 (0 v) vidl7 117 i/o bidirectional expansion port, low byte (bit 7) in 16-bit mode time-multiplexed colour-difference components u and v vidl6 118 i/o bidirectional expansion port, low byte (bit 6) in 16-bit mode time-multiplexed colour-difference components u and v vidl5 119 i/o bidirectional expansion port, low byte (bit 5) in 16-bit mode time-multiplexed colour-difference components u and v vidl4 120 i/o bidirectional expansion port, low byte (bit 4) in 16-bit mode time-multiplexed colour-difference components u and v vidl3 121 i/o bidirectional expansion port, low byte (bit 3) in 16-bit mode time-multiplexed colour-difference components u and v vidl2 122 i/o bidirectional expansion port, low byte (bit 2) in 16-bit mode time-multiplexed colour-difference components u and v vidl1 123 i/o bidirectional expansion port, low byte (bit 1) in 16-bit mode time-multiplexed colour-difference components u and v vidl0 124 i/o bidirectional expansion port, low byte (bit 0) in 16-bit mode time-multiplexed colour-difference components u and v pxqin 125 i pixel quali?er input signal to mark valid pixels; expansion port hin 126 i horizontal sync input signal; expansion port vin 127 i vertical sync input signal; expansion port llcio 128 i/o line-locked system clock input/output; expansion port symbol pin i/o description
1996 sep 04 15 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b fig.4 pin configuration (saa7140b). handbook, full pagewidth mha359 saa7140b 2 1 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 101 102 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 v ssd13 vio v ddd14 v ssd12 v ddd13 fdio vro0 vro1 vro2 vro3 vro4 vro5 vro6 vro7 vro8 vro9 vro10 v ddd12 v ssd11 v ddd11 v ssd10 vro11 vro12 vro13 vro14 vro15 vro16 vro17 vro18 vro19 vro20 vro21 vro22 v ssd9 v ddd10 v ssd8 v ddd9 vro23 v ddd1 llcin v ssd1 v ddd2 llc cref href vs v ddd3 v ssd2 yin0 yin1 yin2 yin3 yin4 yin5 yin6 yin7 v ddd4 v ssd3 uvin0 uvin1 uvin2 uvin3 uvin4 uvin5 uvin6 uvin7 v ddd5 v ssd4 sda scl iicsa v ddd6 v ssd5 v ddd7 v ssd6 port3 40 39 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 127 128 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 vin llcio hin pxqin vidl0 vidl1 vidl2 vidl3 vidl4 vidl5 vidl6 vidl7 v ssd15 v ddd16 v ssd14 v ddd15 vidh0 vidh1 vidh2 vidh3 vidh4 vidh5 vidh6 vidh7 pxqio hio port1 port2 port0 ap sp fldv vsyv hgtv pxqv btst voen v ddd8 vmux v ssd7 hfl incadr vclk vro31 vro30 vro29 vro28 vro27 vro26 vro25 vro24 res
1996 sep 04 16 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 7 functional description the SAA7140A and saa7140b accepts yuv data in a 16-bit wide parallel format at the dmsd port and accepts yuv input in a 16-bit wide parallel format and in an 8-bit byte-multiplexed cb-y-cr-y- format (ccir-656 or d1 oriented) at the expansion port. depending on the selected port modes, the incoming data is formatted to the internal data representation, where reference signals or codes are detected in the data formatter/reformatter (dfr). the horizontal and vertical timing reference can be defined under i 2 c-bus control. based on that timing reference, the active processing window is defined in a versatile way via the programming. two programming sets can be loaded simultaneously, and become valid for processing in a field alternating way. before being processed in the central scaling unit, the incoming data passes through the bcs control unit where monitor control functions, for adjusting brightness, contrast (luminance) and saturation (chrominance) are implemented. the scaling is performed in three steps: 1. horizontal prescaling (bandwidth limitation for anti-aliasing, via fir prefiltering and subsampling) 2. vertical scaling (generating phase interpolated or vertically low-passed lines) 3. horizontal variable phase scaling (phase-correct scaling to the new geometric relationships). the scaled output data is fed back to the dfr unit and may be used as output signals from the bidirectional expansion port (if the mode is selected). they are converted in parallel from the yuv to the rgb domain in a digital matrix. anti-gamma correction of gamma-corrected input signals can be performed in the rgb data path. the output formatter then formats the scaled data to one of the various output formats (e.g. monochrome, 16-bit yuv or 32-bit rgb (5, 5, 5). to ease frame buffer applications, the data can be transferred in a synchronous way (transparent mode), using separate reference and qualifier signals and a continuous output clock (vclk). the data can also be transferred in an asynchronous way (burst mode) using the hfl and incadr flags and a discontinuous input clock burst on vclk. in a typical application, the 16-bit wide yuv input receives clock, sync and data from a video decoder (saa71xx) via the dmsd port. an mpeg compression/decompression circuit can be connected at the expansion port to receive the decoder data, scaled or unscaled, or to deliver data to the scaling processor. the scaling operation of the SAA7140A and saa7140b can be performed on the data from a video decoder, or on the data from the mpeg-codec at the expansion port input. the source selection can be static or toggled on a field-by-field basis. for example, during the odd field the video decoder signal is scaled in accordance with the odd parameter set for display in a window. the compression codec receives unscaled data. during the even field the decompressed data from the mpeg decoder gets sized for a second display window in accordance with the even parameter set. the resulting output from the scaling operation is delivered via the 32-bit wide output (vram port) and to the expansion port output (optional). 7.1 data format/reformatter and reference signal generation the video data can be formatted/reformatted in accordance with the selected expansion port mode, from 16-bit (dmsd port) to serial 8-bit (expansion port output), from serial 8-bit (expansion port input) to internal parallel 16-bit format and from 24-bit (scaler output) to 16-bit/8-bit respectively (expansion port output). the definition of the timing references for the acquisition and field detection (polarity and edge selection) are based on the selected reference signal source. the field detector regenerates the field information from the selected incoming reference signals (see fig.5). the field sequence flag (fld), detects the state of the h-sync signal at the reference edge of the v-sync signal. the detection is controlled by i 2 c-bus bits revfld and invoe. the detection output can be seen on pins fldv and fdio (if fldc = 0). bits iregs and sregs control the mapping of the detected sequence to the i 2 c-bus register sets a and b (i 2 c-bus subaddress 02 to 1f and 22 to 3f).
1996 sep 04 17 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b fig.5 field detection/register set mapping. fld detection modes (i 2 c-bus bits fico1 and fico0); (1) in the normal mode: the fld signal is detected from the incoming h and v signals. in the improved mode: the fld signal is resynchronized only after the h and v sequence runs stable for a certain period of time. in the force toggle mode: the fld signal toggles with every event on the v signal (h is independent). register set mapping modes (i 2 c-bus bits iregs and sregs); the fld_iic signal carries the detected fld or the inverted fld. the signal is fixed to 0 (register set a forced) or forced to 1 (register set a forced). handbook, full pagewidth register 00 field detection (1) source select field detection source select scaler register set mapping field register 00 h/v dmsd h/v expansion port v source select n t m t fido (expansion port) fldv (vram) active vertical edge active horizontal edge h/v source select multiplexer aquisition control register a register b select scaler hv (or frame sync) fld iic h f v f (corresponding to v f ) active horizontal state active vertical edge detected field mha118 invoe revfld 7.1.1 d ata formats and reference signals of the dmsd port the 16-bit yuv colour difference and luminance signals (straight binary) are available in parallel on a 16-bit wide data stream. the code is in accordance with ccir-601; black = 16, white = 235, no colour = 128, 100% colour saturation = 16 to 240 etc. overshoots and undershoots are permitted and supported, i.e. processed as they are. the 16-bit wide yuv data format from the dmsd port (input only) is defined with line-locked clock (llc) with a double pixel clock frequency. every second clock cycle is qualified with cref, in pixel rate frequency. the internal processing of the SAA7140A and saa7140b relies on the presence of llc, i.e. a clock of at least twice the sampling rate of the input data stream. the maximum llc rate is 32 mhz. the horizontal sync input (href) may be supplied as a h-pulse or horizontal gate signal. the positive or negative edge, (programmable by i 2 c-bus bit rehaw), indicates the horizontal timing reference. the first valid pixels may occur not exactly at the start of the line but with a certain offset (counted in qualified pixels).
1996 sep 04 18 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b the vertical timing is indicated by the positive or negative edge (programmable by i 2 c-bus bit revaw) of the sync input signal vs. the first valid line may occur not exactly at the start of the field but with a certain offset, counted in lines, with qualified pixels. input signal vs defines, in relation to href, the odd/even field detection (see saa7191b ). 7.1.2 d ata formats and reference signals of the expansion port the expansion port (input/output) supports several modes; simultaneous (parallel) d1 input and d1 output (full duplex) with auxiliary sync and qualifying signals, or 16-bit wide yuv input or output (half duplex), selected via programming with clock, qualify and sync signal. a discontinuous data stream is supported by accepting or generating a pixel/byte qualifying signal (pxq), a generalization of the cref definition at the dmsd port (pxq = 1 qualified pixel, pxq = 0 invalid data). 16-bit yuv (half duplex mode = field alternating data i/o): 16-bit yuv data stream (y = vidh7 to vidh0, uv = vidl7 to vidl0). for the 16-bit yuv data input format, pxq is inhibited from qualifying adjacent llc clock cycles. there must be at least one empty clock cycle between two valid pixels. 8-bit cb-y-cr-y; ccir 656 or d1 (full duplex mode): the colour difference signals and the luminance signal (straight binary) are byte-wise multiplexed onto the same 8-bit wide data stream, with sequence and timing in accordance with ccir 656 recommendations (according to d1 for 60 hz application respectively). the code is in accordance with ccir 601 (black = 16, white = 235, no colour = 128, 100% colour saturation = 16 or 240, etc. overshoots and undershoots are permitted and supported, i.e. processed as they are. if the ccir 656 output is selected, the video signal is clipped to 01h and feh in order to leave the codes 00h and ffh for sav and eav encoding (sav and eav encoding not yet supported). the clock rate for this format is twice the pixel clock. the horizontal sync input hin is processed in an identical manner to href at the dmsd port. if the ccir 656 data input format is selected, the horizontal timing reference is decoded from the input data stream (sav, eav and shvs = 1) or taken from the selected h-reference signal hin, href or hio (shvs = 0). the start condition to enable synchronization to the correct cb-y-cr-y- sequence is provided by the selected horizontal reference signal. the sequence only increments with qualified bytes. instead of a vertical sync signal, as described for the dmsd port, the expansion port also supports an odd/even signal applied to the input pin vin or vio (controlled by i 2 c-bus bit fsel). the frame and the field timing is then indicated by a positive or negative edge of the v input. this may occur with a certain offset at the frame and field start, and is normally counted in lines. if the ccir 656 data input format is selected, the vertical timing reference is decoded from the input data stream by sav and eav (shvs = 1) or taken from the selected v reference signal vin, vs or vio (shvs = 0). the vertical synchronization pin can be programmed to carry either a vertical sync signal or an odd/even signal. the horizontal and vertical sync outputs hio and vio are expansion port mode dependent and can be selected via the i 2 c-bus (vd1/vd0 and hd1/hd0): should the dmsd port be selected as the output source, hio will carry a copy of href and vio will carry a copy of vs. if the expansion port carries data from the scaler output, then hio is a gate signal enveloping the range of active video along a line and vio is a positive sync pulse with a length of 4 lines if hin/vin is selected as the output source, hio carries a copy of hin and vio carries a copy of vin (short cut). if the ccir 656 data output format is selected, the horizontal and vertical sync output signals are only supplied at pins hio and vio (sav and eav are not encoded as outputs). due to compatibility reasons to the expansion port definition of the saa7194/saa7196 circuits, the bidirectional pins hio, vio and pxqio can also be configured as input pins (see table 3). the definition of the pin fdio is i 2 c-bus selectable. configured as an output pin, fdio carries an odd/even signal generated in the fld detection (see fig.5). configured as an input pin, fdio controls the direction of the expansion port (compatibility to saa7194/saa7196, (see table 3 and chapter 8).
1996 sep 04 19 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b fig.6 timing of pxqin for 16-bit data input from dmsd to expansion port. handbook, full pagewidth llc cref pxqin vidl7 to 0 vidh7 to 0 hin cb0 cr0 cb2 cr2 y0 y1 y2 y3 mha126 fig.7 timing of pxqio for serial 8-bit data input at expansion port. handbook, full pagewidth llc cref pxqin vidl7 to 0 hin cb y y y cr cb mha130
1996 sep 04 20 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b fig.8 timing of pxqin/pxqio for ccir 656 data input at expansion port. handbook, full pagewidth llc cref pxqin/pxqio pxqin/pxqio vidl7 to 0 vidl7 to 0 ffh 00h 00h cb sav y cr y ffh 00h 00h y cr eav mha129 fig.9 timing of pxqio for non-zoomed 16-bit data output at expansion port. handbook, full pagewidth llc cref pxqio vidl7 to 0 vidh7 to 0 hio cb0 cr0 cb2 cr2 y0 y1 y2 y3 mha127
1996 sep 04 21 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b fig.10 timing of pxqin for zoomed 16-bit data output at expansion port. handbook, full pagewidth llc cref pxqio vidl7 to 0 vidh7 to 0 hio cb0 cr0 cb2 cr2 cr4 cb4 y0 y1 y2 y3 y5 y6 y4 cb6 cr6 y7 mha128 fig.11 timing of pxqio for serial 8-bit data output at expansion port. handbook, full pagewidth llc cref pxqio vidl7 to 0 cb y y y cr cb cr y hio mha131
1996 sep 04 22 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 7.2 acquisition control the processing window for the scaling unit is defined in the acquisition control unit. an internal counter receives i 2 c-bus controlled values for offset (bits xo10 to xo0 and yo10 to yo0) and length (bits xs10 to xs0 and ys10 to ys0). the counter is reset by the corresponding sync reference input signal. the horizontal counter increments in qualified pixels and the vertical counter increments in qualified lines, i.e. lines containing at least one qualified pixel. depending on the selected mode, the source for the horizontal reference may be href (dmsd port) or hin (expansion port), or for the vertical reference, vs (dmsd port) or vin (expansion port). it should be noted that in order to avoid programming dependent line and field drop effects, all values must not exceed the number of qualified pixels per line or lines per field. fig.12 reference signals for scaling window. (1) lq = qualified lines i.e. lines containing at least one qualified pixel. handbook, full pagewidth vin/vs pxqv hgtv lq (1) active video window scaling window xs line ys yo xo field/ frame output signals pxq/cref hin/href mha119 7.3 bcs control the parameters for brightness, contrast and saturation (bsc) can be adjusted in the bsc control unit. the luminance signal can be controlled via the i 2 c-bus using bits brig7 to brig0 and cont6 to cont0. for the brightness control: 00h = minimum offset 80h = nominal level ffh = maximum offset. for the contrast control: 00h = luminance off 40h = nominal gain of 1.01 7fh = maximum gain of 1.9999. the chrominance signal can be controlled via the i 2 c-bus using bits sat6 to sat0. for the saturation control: 00h = colour off 40h = nominal gain of 1.0 7fh = maximum gain of 1.9999.
1996 sep 04 23 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b with respect to limiting, all values are limited to minimum (equals 0) and maximum (equals 255). 7.4 scaling unit scaling to a randomly sized window is performed in three steps: 1. horizontal prescaling (bandwidth limitation for anti-aliasing, via fir prefiltering and subsampling) 2. vertical scaling (generating phase interpolated or vertically low-passed lines) 3. horizontal variable phase scaling (phase-correct scaling to the new geometric relations). the scaling processor can obtain its clock from the dmsd port or the expansion port. normally the two ports are synchronized to support program-set-swapping, asynchronous working results in restricted operation. the video signal source also provides the source for the scalers qualify signal pxq. the scaling process generates a new pixel/clock qualifier sequence. this results in pxq being used at the vram port in the transparent mode, and for the expansion port output. there are restrictions in the combination of the input sample rate and up or down-scaling mode and scaling factor. the maximum resulting output sample rate at the vram port is llc and at the expansion port the maximum pixel rate is 1 2 llc, due to the support of the ccir 656 format. 7.4.1 h orizontal prescaling the incoming pixels in the selected range are preprocessed in the horizontal prescaler, which is the first stage of the scaling unit. the prescaler consists of an fir prefilter and a pixel collecting subsampler. 7.4.1.1 fir pre?lter the video components y, u and v are fir prefiltered to reduce the signal bandwidth in accordance with the downscale for factors between 1 to 1 2 , thus aliasing due to signal bandwidth expansion is reduced. the prefilter consists of 3 filter stages. the transfer functions are given in chapter 8. the prefilter is controlled by the i 2 c-bus bits pfy3 to 0 and pfuv3 to 0 in i 2 c-bus subaddress 13 and 33. figures 13 and 14 illustrate some frequency responses and the corresponding i 2 c-bus settings. the prefilter operates on 4 :4:4 yuv data. as u and v are generated by simple chroma pixel doubling, the uv prefilter should also be used to generate the interpolated chroma values. 7.4.1.2 subsampler to improve the scaling performance for scales of less than 1 2 down to icon size, a fir filtering subsampler is available. it performs a subsampling of the incoming data by a factor of 1/n (where n = xpsc + 1 = 1 to 64). with n ip equalling the number of input pixel/line and n op equalling the number of desired output pixels/line, the basic equation to calculate xpsc is as follows: the subsampler collects a number of [n + 1( - xacm)] pixels to calculate a new subsampled output pixel. consequently, a downscale dependent fir filter has been incorporated, with up to 65 taps, which reduces aliasing for small sizes. if xacm = 0 the collecting sequence overlaps, which means that the last pixel of sequence m is also the first pixel of sequence m + 1. to implement a real subsampler bypass xacm has to be set to logic 1. it should be noted that because the phase-correct horizontal fine scaling is limited to a maximum downscale of 1 4 , this circuitry has to be used for downscales less than 1 4 of the incoming pixel count. to obtain unity gain at the subsamplers output for all subsampling ratios, the i 2 c-bus parameters cxy, cxuv and dcgx have to be used. in addition, the i 2 c-bus parameters can be used to slightly modify the fir characteristic of the subsampler. table 1 gives examples of i 2 c-bus register settings, depending on a given prescaler ratio. with reference to table 1, it should be noted that an internal xpsc-dependent automatic prenormalization becomes valid for xpsc > 8, > 6 and >32, which reduces the input signal quantization. in addition, for xpsc 3 15 the lsb of the cxy and cxuv parameter become valid. xpsc trunc n ip n op 1 C -------------------- ? ? ?? =
1996 sep 04 24 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b fig.13 luminance prefilter frequency response for miscellaneous i 2 c-bus settings. handbook, full pagewidth 0.5 18 ?2 0 0.1 0.2 0.3 0.4 mha121 ?0 ?8 ? 6 0 (gain) db (1) (2) (3) (4) (5) f f clk i 2 c-bus bytes pfy3 to pfy0. (1) = 0001; (2) = 0010; (3) = 0011; (4) = 1011; (5) = 1111. fig.14 chrominance prefilter frequency response for miscellaneous i 2 c-bus settings. handbook, full pagewidth 0.5 18 ?2 0 0.1 0.2 0.3 0.4 f f clk mha122 ?0 ?8 ? 6 0 (gain) db (1) (2) (3) (4) (5) (6) i 2 c-bus bytes pfu3 to pfu0. (1) = 0001; (2) = 0010; (3) = 1010; (4) = 1110; (5) = 0011; (6) = 1111.
1996 sep 04 25 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 1 horizontal prescaling and normalization horizontal prescaling xpsc coefficient sequence (example) cxy (luma)/ cxuv (chroma) (hex) weight sum dcgx bsc (cont/sat) =x/y 64 1 0 1-1 00 2 1 1 1 2 1 1-1-1 00 3 1 2 3 1-2-1 02 4 2 1 1 3 2 1-1-1-1 00 4 2 1 1 4 3 1-1-1-1-1 00 5 2 4 5 1-2-2-2-1 06 8 3 1 1 5 4111111 0062 4 6 121 121 02 8 3 1 112 211 04 8 3 1 1 6 5 1111111 00 7 3 8 7 1112111 08 8 3 1 1 7 611111111 00831 1 8 7 111111111 00 9 3 8 9 1222 2 2221 1e 16 7 1 1 9 8 1111111111 00 10 2 2 4 5 1221 2 2 1221 16 16 2 31 1122 2 2 2211 1c 16 2 31 1 10 9 11111111111 00 11 2 2 8 11 1212 1 2 1 2121 2a 16 2 31 11122222111 38 16 2 31 1 11 10 1111 11 11 1111 00 12 2 2 8 12 1211 21 12 1121 12 16 2 31 1111 22 22 1111 30 16 2 31 1 12 11 1111 11 1 11 1111 00 13 2 2 8 13 1121 11 2 11 1211 44 16 2 31 1111 12 2 21 1111 60 16 2 31 1 13 12 11111111111111 00 14 2 2 8 14 1111 211 112 1111 10 16 2 31 1111 112 221 1111 40 16 2 31 1 14 13 1111 111 1 111 1111 00 15 2 2 8 15 1111 111 2 111 1111 80 16 2 31 1 15 14 1111 1111 1111 1111 00 16 2 31 1 16 15 1111 1111 1 1111 1111 17 2 3 16 17 1222 2222 2 2222 2221 ff 32 2 71 1 17 16 1111 1111 1 1 1111 1111 00 18 4 2 16 18 1222 2222 1 1 2222 2221 fe 32 4 31 1222 2122 22 2212 2221 df 32 4 31
1996 sep 04 26 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 1 18 17 1111111111111111111 00 19 4 2 16 19 1222 1222 1 2 1 2221 2221 ee 32 4 31 1222 211 22222112 2221 9f 32 4 31 .... .... .... .... xx 4 .... .... 1 33 32 1111 ... 1111 00 34 8 2 - .... .... .... .... xx 8 .... .... 1 63 62 .... .... .... .... .... 1 64 63 .... .... .... .... .... horizontal prescaling xpsc coefficient sequence (example) cxy (luma)/ cxuv (chroma) (hex) weight sum dcgx bsc (cont/sat) =x/y 64 7.4.2 v ertical scaler the vertical scaler performs the vertical downscaling of the input data stream to a random number of output lines. it can be used for input line lengths up to 768 pixels/line and has to be bypassed if the input line length exceeds the pixel count. for vertical scaling there are two different modes implemented; the accu mode (vertical accumulation) for scales down to icon size and the linear phase interpolation mode (lpi) for scales between 1 and 1 2 . 7.4.2.1 accu mode (scaling factor range 1 to 1/1024; i 2 c-bus bit yacm = 1: the accu mode can be used for vertical scaling down to icon size. in this mode, the i 2 c-bus parameter ysci controls the scaling and parameter yacl controls the vertical anti-alias filtering. the output lines are generated by a scale-dependent variable averaging (yacl + 2) input lines. in this way a vertical fir filter can be created for anti-aliasing, with up to 65 taps (max.). ysci defines the output line qualifier pattern and yacl defines the sequence length for the line averaging. for accurate processing, the sequence has to fit into the qualifying pattern. in the event of mis-programming yacl unexpected line dropping occurs; where n ol = number of output lines and n il = number of input lines. the i 2 c-bus bits ysci (scaling increment), yacl (accumulation length; optimum: 1 line overlap) and yp (scaling start phase) have to be set according to the following equations (see fig.15): ; accumulation sequence length: i.e. the number of lines per sequence that are not part of overlay region of neighbouring sequences (optimum 1 line overlapped). ; scaling increment. ; scaling start phase (fix; modified in lpi mode only). in order to obtain unity amplitude gain for all sequence lengths and to improve the vertical scaling performance, the accumulated lines can be weighted and the amplitude of the scaled output signal has to be renormalized. in the given example (see fig.15) using the optimum weighting, the gain of a sequence results in 1 + 2 + 2+1=6. renormalization (factor 1/6) can be achieved; by gain reduction using bcs control (brightness, contrast and saturation) down to 4 6 and a selecting factor of 1 4 for dcgy2 to dcgy0 (see section 8.3), which may result in a loss of signal quantization, or by gain emphasizing using bcs control up to 8 6 and selecting a factor of 1 8 for dgy2 to dcgy0 which may result in a loss of signal detail, due to limiting in the bcs control. normally the weighting would be 2 + 2 + 2 + 2. in this situation the gain can be renormalized with dcgy2 to dcgy0 = 010 (factor 1 8 ). table 2 gives examples for i 2 c-bus register settings, depending on a given scale ratio. yacl trunc n il n ol 1 C ------------------- - ? ? ?? = ysci int 1024 1n ol C n il ------------------- - ? ? ?? = yp int ysci 16 -------------- - ? ?? =
1996 sep 04 27 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b fig.15 example of vertical accumulation. handbook, full pagewidth optimal weighting factors: line 1 line 2 line 10 1st sequence 2nd sequence 3rd s equence 1 2 2 1 2 2 1 2 2 1 yacl = int{(1-s)/s} = 2 (dotted lines) ysci = int{(1024 (1-s)} = 682 yp = int{ysci/16} = 42 mha120 table 2 vertical scaling and normalization vertical scale ratio (ysci 3 3 ) yacl coefficient sequence (example) cya (hex) cyb (hex) weight sum dcgy bcs (cont/sat) = x/y 64 1to 1 2 (0) 0 1-1 01 00 2 0 1 1 2 to 1 3 (512) 1 1-1-1 03 00 3 0 2 3 1-2-1 01 02 4 1 1 1 3 to 1 4 (683) 2 1-1-1-1 03 00 4 1 1 1 4 to 1 5 (768) 3 1-1-1-1-1 07 00 5 1 4 5 1-2-2-2-1 01 06 8 2 1 1 5 to 1 6 (820) 4111111070061 4 6 121 121 05 02 8 2 1 112 211 03 04 8 2 1 1 6 to 1 7 (854) 5 111 1 111 0f 00 7 2 8 7 111 2 111 07 08 8 2 1 1 7 to 1 8 (878) 6 1111 1111 0f 00 8 2 1 1 8 to 1 9 (896) 7 111111111 1f 00 9 2 8 9 1222 2 2221 01 1e 16 3 1 1 9 to 1 10 (911) 8 1111111111 1f 00 10 3 8 10 2121 2 2 1212 09 15 16 3 1 1122 2 2 2211 03 1c 16 3 1 1 10 to 1 11 (922) 9 111111 11111 3f 00 11 2 8 11 1212121 2121 15 2a 16 3 1 11122222111 07 38 16 3 1 1 11 to 1 12 (931) 10 1111 11 11 1111 3f 00 12 2 8 12 1211 21 12 1121 2d 12 16 3 1 1111 22 22 1111 0f 30 16 3 1
1996 sep 04 28 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 1 12 to 1 13 (939) 11 1111111111111 7f 00 13 2 8 13 1111 21 2 12 1111 2f 50 16 3 1 1121 11 2 11 1211 3b 44 16 3 1 1 13 to 1 14 (946) 12 1111 111 111 1111 7f 00 14 2 8 14 1111 211 112 1111 6f 10 16 3 1 1111 112 211 1111 3f 40 16 3 1 1 14 to 1 15 (951) 13 1111 111 1 111 1111 ff 00 15 2 8 15 1111 111 2 111 1111 7f 80 16 3 1 1 15 to 1 16 (956) 14 1111 1111 1111 1111 ff 00 16 3 1 1 16 to 1 17 (960) 15 1111 1111 1 1111 1111 ff 00 17 3 16 17 2122 2222 2 2222 2212 02 fd 32 4 1 1 17 to 1 18 (964) 16 111111111111111111 ff 00 18 3 16 18 2212 221 2 2 2 2122 2122 44 bb 32 4 1 1222 222 2 1 1 2222 2221 01 fe 32 4 1 .... .... .... .... .... .... .... .... 1 23 to 1 24 (980) 22 1111 2222 1111 1111 2222 1111 0f f0 32 4 1 1121 1212 1121 1211 2121 1211 ad 52 32 4 1 vertical scale ratio (ysci 3 3 ) yacl coefficient sequence (example) cya (hex) cyb (hex) weight sum dcgy bcs (cont/sat) = x/y 64 7.4.2.2 lpi mode (scaling factor range 1 to 1 2 ; ic-bus bit yacm = 0) to preserve the signal quality for slight vertical downscales (scaling factors 1 to 1 2 ) linear phase interpolation between consecutive lines is implemented to generate geometrically correct vertical output lines.therefore, the new geometric position between lines n and n + 1 can be calculated. a new output line is calculated by weighting the samples p (pixel) of lines n and n + 1 with the normalized distance to the new calculated position (see fig.16); when n ol = number of output lines and n il = number of input lines the i 2 c-bus bits ysci (scaling increment) and yp (scaling start phase) have to be set according to the following equations; fig.16 new output line calculation. where a = 0 to 63/64 pm () apn1 + () 1a C () pn () + = handbook, halfpage mha361 input lines new calculated position of output line m n distance = 1 n + 1 aa - 1 m
1996 sep 04 29 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b ; scaling increment ; scaling start phase (recommended value). the vertical start phase offset is defined by yp 64 (yp = 0 to 64): yp = 0: offset = 0 geometrical position of 1st line out = 1st line in. yp = 64: offset = 64 64 = 1 geometrical position of 1st line out = 2nd line in. finally 3 special modes must be emphasized: 1. by-pass (ysci = 0, yp = 64) each line out is equivalent to corresponding line in. 2. low-pass (ysci = 0, yp < 64) e.g. yp = 32: average value of 2 lines (1 + z - h filter). 3. for processing of interlaced input signals the lpi mode must be used (the accu mode would cause line pairing problems). the scaling start phase for odd and even field have to be set to: ; where line 1 = odd. in modes 1 and 2 the first input line is fed to the output (without processing) so that the number of output lines equals the number of input lines. 7.4.2.3 flip option (flip = 1) for both vertical scaling modes there is a flip option (mirroring) available for input lines with a maximum of 384 pixels. in the event that full screen pictures (e.g. 768 576) are to be flipped, they first have to be scaled down to 384 pixels per line in the horizontal prescaling unit. after vertical processing (flipping) they can be rezoomed to the original 768 pixels per line in the following vpd. it should be noted that when using the flip option, the last input line can not be displayed at the output. 7.4.3 h orizontal variable phase scaling in the phase-correct horizontal variable phase scaling the pixels are calculated for the geometrical correct, orthogonal output pattern, down to 1 4 of the prescaled pattern. in addition, a horizontal zooming feature is supported. the maximum zooming factor is at least 2, thus being even more dependent on input pattern and prescaling settings. ysci int 1024 n il n ol ---------- 1 C ? ? ?? = yp int ysci 16 -------------- - ? ?? = yp even yp odd ysci 32 -------------- - + = the phase scaling consists of a filter and arithmetic structure with 10 taps for the luminance and 4 taps for the chrominance processing. it is able to generate a phase-correct new pixel value, with virtually no phase or amplitude artefacts. the new samples are calculated with a phase accuracy of 1 64 of the pixel distance. when using this circuit the up and down scaling is controlled by the i 2 c-bus parameters xsci and xp. because the variable phase scaling is restricted to downscale > 1 4 of the fine scalers input pixel count, xsci is also a function of the prescaling parameter xpsc. as n ip = number of input pixels per line (at SAA7140A input) and n op = number of desired output pixels/line, xsci is defined by the following equation: the maximum value of xsci = 4095. zooming is performed for xsci values less than 1024. the number of disqualified clock cycles between consecutive pixel qualifiers (at the phase scalers input) defines the maximum possible zoom factor. this means that zooming may also be a function of xpsc. it should be noted that implementation is dependent on a zooming factor greater than 2. some artefacts may occur at the end of the zoomed line. internal rounding effects, may result in a deviation of 1 output pixels compared to the expected result. in this situation, the i 2 c-bus parameter xp can be used to shift the starting phase of the phase calculation and thereby force an additional cycle to be disqualified. in addition, when xp 3 128 it will force the internal phase calculation to fixed values, especially when xp = 128 it will force the phase scaler into bypass. the scaled output data is fed back to the data formatter/reformatter unit and may be used as output signals from the bidirectional expansion port (if the mode is selected). 7.5 colour space matrix (csm), dither and gamma correction the scaled yuv output data can be converted after interpolation into rgb data in accordance with ccir 601 recommendations. xsci int n ip n op ---------- - 1024 xpsc 1 + () --------------------------------- - =
1996 sep 04 30 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b the matrix equations considering the digital quantization are as follows; r = y + 1.375 v g=y - 0.703125 v - 0.34375 u b = y + 1.734375 u for error diffusion a dither algorithm of the 5-bit truncation error rgb (5, 5, 5) is implemented. an anti-gamma characteristic ( g = 1.4) is implemented at the matrix output to provide anti-gamma correction of the rgb data. the curve can be used (bit rtb = 0) to compensate gamma correction for linear data representation of the rgb output data. the chroma signal keyer generates an alpha signal to achieve an rgb (5, 5, 5) + a output signal. therefore, the processed uv data amplitudes are compared with thresholds set via the i 2 c-bus. a logic 1 signal is generated if the amplitude is within the specified amplitude range, if the amplitude is outside the specified range a logic 0 is generated. keying can be switched off by setting the lower limit higher than the upper limit. for 16-bit yuv data formats or monochrome modes the csm block is bypassed. 7.6 output formatter and output fifo register in order to support various scaling applications, the output data at the vram port can be delivered in different formats and different transfer modes. besides the 16-bit yuv format (see section 7.1.1) the vram port also supports the data formats 24-bit rgb, 2 15-bit rgb + a or 8-bit grey scale. should the synchronous data transfer mode (transparent mode) be selected, the vram port will provide vclk clock (clock rate of llc) and pxq (polarity via programming) on extra pins for use by the circuitry receiving the vram port data stream. to ease frame buffer applications, an asynchronous transfer (burst or fifo mode) can be selected. in this mode the vram ports vclk has to be provided from an external source, with a maximum clock rate of 32 mhz. only valid data is collected and transported. 7.6.1 d ata formats and reference signals of the vram port 7.6.1.1 16-bit yuv (see section 7.1.1) the ordering of yuv bits and bytes at the vram port is identical to that of the saa7196. 7.6.1.2 24-bit rgb: the resampled yuv samples are converted into rgb (8 bits each). all three components have the same sample rate as luminance y. anti-gamma correction is available (programming). the alpha bit is generated as the chroma key in the uv domain. two rgb representations (code meanings) are supported: 1. the ccir 601 orientated rgb representation defines code 16 for black and code 235 for full saturation. 2. the graphics display orientated rgb representation codes black with 00h and white with ffh. this representation can be achieved by corresponding programming of brightness (equals offset), contrast and saturation (equals gain) in the yuv domain. this format is used in the transparent mode and in the fifo mode (one pixel at a time). 7.6.1.3 15-bit rgb (5, 5, 5) + a in 2 bytes the resampled yuv samples are converted into 24-bit rgb. the following truncation to 5 bits is optionally (programming) performed with dithering effect (error diffusion). there are two representations (code meanings) supported; ccir and graphics display orientated (see section 7.6.1.2). the alpha bit is generated as chroma key in the yuv domain. this format is used in the transparent mode and in the fifo mode (one pixel at a time, or two pixels at a time). the ordering of rgb bits and bytes at the vram port is identical to that of the saa7196. 7.6.1.4 8-bit grey scale this is simply a y = luminance signal which can be selected to be coded as binary, or all bits inverted. this format is used in the transparent mode and in the fifo mode (1, 2 or 4 pixels at a time). the horizontal sync output hgtv marks (source independent) the range of the active video at the vram port. the vertical sync output vsyv (i 2 c-bus controlled polarity) carries the vertical sync information for the vram port output data (positive or negative pulse with a length of 4 lines). at the falling or rising edge of vsyv the fldv output is stable.
1996 sep 04 31 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b fig.17 output port transfer to vram at 32-bit data format without scaling. if vclk cycles occur at voen = high the fifo register is unchanged but the outputs vro31 to vro0 remain in the 3-state position. (1) only valid for non-zoomed data. handbook, full pagewidth minimum 8 words available in fifo maximum 32llc (1) (16 pixclk) 1 transfer cycle (8 vclk cycles) 70 1 2 3 4 5 6 7 78988766544 pixclk (llc/2) fifo memory filling level hfl vclk voen vro(n) mha132 fig.18 vertical reset timing of the vram port. (1) only available for interfaced processing at the beginning of an odd field. handbook, full pagewidth vertical blanking active video last half-full request for line n (1) (1) line n internal signal line n + 1 64llc line increment sequence (1) vertical reset pulse 10llc 64llc minimum set-up time hfl incadr mha123
1996 sep 04 32 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 7.7 data transfer modes 7.7.1 e xpansion port modes the expansion port is controlled by i 2 c-bus subaddresses 02 (22h) and 03 (23h). the expansion port can be configured in a very flexible way. table 3 gives examples of the i 2 c-bus programming for several expansion port configurations. saa7196 compatible modes are marked as xx96 in the mode column. after reset the expansion port reference signal inputs are set to the xxio pins. after reset the expansion port reference signal inputs are set to the xxio pins. pin fdio can be used in the same way as the dir pin of the saa7196 if the i 2 c-bus bit fldc is set to logic 1. more information concerning the control signals can be found in chapter 8. for correct application the user should first decide about some global interface properties before referring to this chapter such as: does the application require separate input and output reference signal lines, if yes then i 2 c-bus bit srio = 0 does the application need hardware controlled i/o switching, if yes then i 2 c-bus bit fldc = 1 and use of pin fdio or does software controlled i/o switching (register set controlled) the same job, if yes then i 2 c-bus bit fldc = 0 which signal path defines the clock system which signal path is the synchronization master is dynamic field-wise switching required or is the source switching quite static, if static then do not be confused about odd or even; use sregs and iregs before referring to the i 2 c-bus section.
1996 sep 04 33 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 3 expansion port programming examples notes 1. scaler input from llc, y/uvin, cref, href and vs; expansion port output clock, data, qualifier, horizontal and vertical reference derived from llc, y/uvin, cref, href and vs. 2. scaler input from llc, vidh|l, pxqin, href and vs; expansion port output clock, data, qualifier, horizontal and vertical reference derived from llc, d.c., cref, href and vs. 3. scaler input from llcin, vidh|l, pxqin, hin and vin; expansion port output clock, data, qualifier, horizontal and vertical reference derived from llcin, d.c., cref, hin and vin. 4. scaler input from llc, vidh|l, pxqin, hin and vin; expansion port output clock, data, qualifier, horizontal and vertical reference derived from llc, d.c., cref, hin and vin. mode fdio dave output control [subaddress 02 (22h)] scaler input control [subaddress 03 (23h)] i/o yuv8 04 to 24h fldc vidc vd1 vd0 hd1 hd0 pxqd llcd srio vsi hsi vipsi llcs 0 x 0 00000000 00000 note 1 1 x 0 01000000 00010 note 2 2 x 0 01x1x10101111 note 3 3 x 0 01x1x10001110 note 4 4 x 0 00101010 00000 note 5 5 x 1 00101010 00010 note 6 6 x 1 00000000 01111 note 7 7 x 1 00101011 01111 note 8 8 x 0 01000000 00110 note 9 9 x 1 0 1xxxxxx 11111 note 10 0960 0 10000000 10000 note 11 1961 0 10000000 10000 note 12 2961 0 1 1 xxxxxx 11111 note 13 396x 0 11xxx10011100 note 14 4961 0 1100xxx0 10110 note 15 5960 0 1000xxx0 10011 note 16 6961 0 1000xxx0 10011 note 17 note 18
1996 sep 04 34 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 5. scaler input from llc, y|uvin, cref, href and vs; expansion port output clock, data, qualifier, horizontal and vertical reference derived from llc, yuvsc, psc, hsc and vsc. 6. scaler input from llc, vidl, pxqin, href and vs; expansion port output clock, data, qualifier, horizontal and vertical reference derived from llc, yuvsc->vidh, psc, hsc and vsc. 7. scaler input from llcin, vidl, pxqin, hin and vin; expansion port output clock, data, qualifier, horizontal and vertical reference derived from llc, y|uvin->vidh, c+href and vs. 8. scaler input from llcin, vidl pxqin, hin and vin; expansion port output clock, data, qualifier, horizontal and vertical reference derived from llcin, yuvsc->vidh, psc, hsc and vsc. 9. scaler input from llc, vidh|l pxqin, hin and vs; expansion port output clock, data, qualifier, horizontal and vertical reference derived from llc, d.c., cref, href and vs. 10. scaler input from llcio, vidh, pxqio, hio and vio; expansion port output clock, data, qualifier, horizontal and vertical reference derived from d.c., d.c., d.c., d.c. and d.c.. 11. scaler input from llc, y|uvin, cref, href and vs; expansion port output clock, data, qualifier, horizontal and vertical reference derived from llc, y|uvin, cref, href and vs. 12. scaler input from llc, vidh|l, cref, href and vs; expansion port output clock, data, qualifier, horizontal and vertical reference derived from llc, d.c., cref, href and vs. 13. scaler input from llcio, vidh|l, pxqio, hio and vio; expansion port output clock, data, qualifier, horizontal and vertical reference derived from d.c., d.c., d.c., d.c. and d.c.. 14. scaler input from llc, vidh|l, cref, hio and vio; expansion port output clock, data, qualifier, horizontal and vertical reference derived from llc, d.c., cref, d.c. and d.c. 15. scaler input from llc, vidh/l, pxqio, hio and vs; expansion port output clock, data, qualifier, horizontal and vertical reference derived from llc, d.c., d.c., d.c., href and vs. 16. scaler input from llc, y/uvin, cref, href and vs; expansion port output clock, data, qualifier, horizontal and vertical reference derived from llc, y/uvin, cref, href and vs. 17. scaler input from llcio, vidh/l, pxqio, href and vs; expansion port output clock, data, qualifier, horizontal and vertical reference derived from d.c., d.c., d.c., href and vs. 18. fill in user specific configuration.
1996 sep 04 35 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 7.8 vram port modes 7.8.1 d ata burst transfer mode (fifo m ode ) data transfer on the vram port is asynchronous (ttr = 0). this mode can be used for all output formats. four signals for communication with the external memory are provided: 1. hfl flag: the half-full flag of the fifo output register is raised when the fifo contains at least 8 data words (hfl = high). by setting hfl to logic 1, the SAA7140A and saa7140b requests a data burst transfer, via the external memory controller, that has to start a transfer cycle within the next 32llc cycles for 32-bit long word modes (16llc cycles for 16 and 24-bit modes). if there are pixels in the fifo at the end of the line, which are not transferred, the circuit fills up the fifo register with fill pixels until it is half-full and sets the hfl flag to request a data burst transfer. after the transfer is completed, hfl is used in combination with incadr to indicate the line increments. 2. the incadr output signal is used in combination with hfl to control horizontal and vertical address generation for a memory controller. the pulse sequence depends on field formats (interlace/non-interlace or odd/even fields) and control bits of1 and of0 (subaddress 01). this means that: a) hfl = 1 at the rising edge of incadr: the end of line is reached; request for line address increment b) hfl = 0 at the rising edge of incadr: the end of field/frame is reached; request for line and pixel address reset 3. vclk input signal to clock the fifo register output data vro(n). new data is placed on the vro(n) port with the rising edge of vclk (see fig.17). 4. the voen input enables output data vro(n). the outputs are in 3-state mode at voen = high. voen changes only when vclk is low. if vclk pulses are applied when voen is high, the outputs remain inactive but the fifo register accepts the pulses. 7.8.2 c ontinuous data transfer mode ( transparent mode ) data transfer on the vram port can be achieved synchronously (ttr = 1), controlled by output reference signals at separate pins (except the a -signal) and a continuous clock output signal (clock rate of llc) on the vclk pin. the SAA7140A and saa7140b delivers a continuously processed data stream. consequently, the extended formats of the vram port output are selected (bit fs2 = 1; see tables 6 and 7). the output reference signals have to be used to buffer qualified preprocessed rgb or yuv video data. the yuv data is only valid in qualified time slots. control output signals (see tables 6 and 7) are: a = keying signal of the chroma keyer (not on extra pin but in lower byte of vro output) fldv = odd/even field bit in accordance with the internal field processing vsyv = vertical sync signal, active polarity is defined by vsyp bit hgtv = horizontal gate signal, logic 1 marks the horizontal direction from xo to (xo + xs) lines pxqv = pixel qualifier signal, active polarity is defined by qpp bit. interlaced processing (of bits, subaddress 01): to support correctly interlaced data storage, the scaler delivers two incadr/hfl sequences in each qualified line and an additional incadr/hfl sequence after the vertical reset sequence at the beginning of an odd field. consequently, the scaled lines are automatically stored in the right sequence. incadr timing: the distance from the last half-full request (hfl) to the incadr pulse may be longer than 64llc. the state of hfl is defined for minimum 2llc cycles afterwards. monochrome format (see tables 6 and 7); if ttr = 1 and fs2 = 1 then ya = yb. 7.8.3 i 2 c- bus controlled pseudo sleep mode to reduce the power consumption of the SAA7140A and saa7140b during phases, where no scaling operations are requested in the application, it is possible to switch the SAA7140A and saa7140b into a pseudo sleep mode. this mode can be activated, if the clock input llcin is not used or if the hardware is able to pull the llcin input or the llcio pin (in input mode) down to logic 0. in applications, which do not use llcin, then llcin should be connected to ground. llc has to be provided continuously.
1996 sep 04 36 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b to activate the sleep mode the scalers processing has to be switched to one of the inactive clock inputs of the expansion port. for example, if llcio is used as input and output in the application then: llcin grounded => sleep mode is active, if i 2 c-bus bits fldc = 0, srio = 0 and llcs = 1. and if llcin is used as input and llcio is used as output: llcin pulled down => sleep mode is active, if i 2 c-bus bits fldc = 0, srio = 0 and llcs = 1. llcio pulled down => sleep mode is active, if i 2 c-bus bits fldc = 0, srio = 1 and llcs = 1. to activate the scaler again, switch back to an active input clock, via srio and/or llcs. in sleep mode the power consumption of the SAA7140A and saa7140b is reduced to approximately 15% of its normal operational value. table 4 vram port output data formats (vro31 to vro16) at fs2 bit = 0 and vof bit = 1 (can be set via i 2 c-bus), burst mode only, pixel order = n, n + 1, n + 2, etc. notes 1. a = keying bit. 2. rgb and yuv = digital signals. 3. e = even pixel numbers. 4. a and b = consecutive pixels. pixel output bits fs1 = 0; fs0 = 0 rgb (5 , 5 , 5) + a 32-bit words (1)(2) fs1 = 0; fs0 = 1 yuv4:2:2 32-bit words (2)(3) fs1 = 1; fs0 = 0 yuv4:2:2 16-bit words (2)(3) fs1 = 1; fs0 = 1 8-bit monochrome 32-bit words (4) n n+2 n+4 n n+2 n+4 n n+1 n+2 n n+1 n+4 n+5 n+8 n+9 vro31 aaa y e7 y e7 y e7 y e7 y o7 y e7 y a7 y a7 y a7 vro30 r4 r4 r4 y e6 y e6 y e6 y e6 y o6 y e6 y a6 y a6 y a6 vro29 r3 r3 r3 y e5 y e5 y e5 y e5 y o5 y e5 y a5 y a5 y a5 vro28 r2 r2 r2 y e4 y e4 y e4 y e4 y o4 y e4 y a4 y a4 y a4 vro27 r1 r1 r1 y e3 y e3 y e3 y e3 y o3 y e3 y a3 y a3 y a3 vro26 r0 r0 r0 y e2 y e2 y e2 y e2 y o2 y e2 y a2 y a2 y a2 vro25 g4 g4 g4 y e1 y e1 y e1 y e1 y o1 y e1 y a1 y a1 y a1 vro24 g3 g3 g3 y e0 y e0 y e0 y e0 y o0 y e0 y a0 y a0 y a0 vro23 g2 g2 g2 u e7 u e7 u e7 u e7 v e7 u e7 y b7 y b7 y b7 vro22 g1 g1 g1 u e6 u e6 u e6 u e6 v e6 u e6 y b6 y b6 y b6 vro21 g0 g0 g0 u e5 u e5 u e5 u e5 v e5 u e5 y b5 y b5 y b5 vro20 b4 b4 b4 u e4 u e4 u e4 u e4 v e4 u e4 y b4 y b4 y b4 vro19 b3 b3 b3 u e3 u e3 u e3 u e3 v e3 u e3 y b3 y b3 y b3 vro18 b2 b2 b2 u e2 u e2 u e2 u e2 v e2 u e2 y b2 y b2 y b2 vro17 b1 b1 b1 u e1 u e1 u e1 u e1 v e1 u e1 y b1 y b1 y b1 vro16 b0 b0 b0 u e0 u e0 u e0 u e0 v e0 u e0 y b0 y b0 y b0
1996 sep 04 37 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 5 vram port output data formats (vro15 to vro0) at fs2 bit = 0 and vof bit = 1 (can be set via i 2 c-bus), burst mode only, pixel order = n, 1n, 2n, etc. notes 1. a = keying bit. 2. rgb and yuv = digital signals. 3. o = odd pixel numbers. 4. e = even pixel numbers. 5. c and d = consecutive pixels. pixel output bits fs1 = 0; fs0 = 0 rgb (5 , 5 , 5) + a 32-bit words (1)(2) fs1 = 0; fs0 = 1 yuv4:2:2 32-bit words (2)(3)(4) fs1 = 1; fs0 = 0 yuv4:2:2 16-bit words (2) fs1 = 1; fs0 = 1 8-bit monochrome 32-bit words (5) n + 1 n + 3 n + 5 n + 1 n + 3 n + 5 output not used n+2 n+3 n+6 n+7 n+10 n+11 vro15 aaa y o7 y o7 y o7 xxxy c7 y c7 y c7 vro14 r4 r4 r4 y o6 y o6 y o6 xxxy c6 y c6 y c6 vro13 r3 r3 r3 y o5 y o5 y o5 xxxy c5 y c5 y c5 vro12 r2 r2 r2 y o4 y o4 y o4 xxxy c4 y c4 y c4 vro11 r1 r1 r1 y o3 y o3 y o3 xxxy c3 y c3 y c3 vro10 r0 r0 r0 y o2 y o2 y o2 xxxy c2 y c2 y c2 vro9 g4 g4 g4 y o1 y o1 y o1 xxxy c1 y c1 y c1 vro8 g3 g3 g3 y o0 y o0 y o0 xxxy c0 y c0 y c0 vro7 g2 g2 g2 v e7 v e7 v e7 xxxy d7 y d7 y d7 vro6 g1 g1 g1 v e6 v e6 v e6 xxxy d6 y d6 y d6 vro5 g0 g0 g0 v e5 v e5 v e5 xxxy d5 y d5 y d5 vro4 b4 b4 b4 v e4 v e4 v e4 xxxy d4 y d4 y d4 vro3 b3 b3 b3 v e3 v e3 v e3 xxxy d3 y d3 y d3 vro2 b2 b2 b2 v e2 v e2 v e2 xxxy d2 y d2 y d2 vro1 b1 b1 b1 v e1 v e1 v e1 xxxy d1 y d1 y d1 vro0 b0 b0 b0 v e0 v e0 v e0 xxxy d0 y d0 y d0
1996 sep 04 38 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 6 vram port output data formats (vro31 to vro16) at fs2 bit = 1 and vof bit = 1 (can be set via i 2 c-bus), burst and transparent mode, pixel order = n, n + 1, n + 2, etc. notes 1. a = keying bit. 2. rgb and yuv = digital signals. 3. e = even pixel numbers. 4. a and b = consecutive pixels. pixel output bits fs1 = 0; fs0 = 0 rgb (5 , 5 , 5) + a 16-bit words (1)(2) fs1 = 0; fs0 = 1 yuv4:2:2 16-bit words (2)(3) fs1 = 1; fs0 = 0 rgb (8 , 8 , 8) 24-bit words (2) fs1 = 1; fs0 = 1 8-bit monochrome 16-bit words (4) n n+1 n+2 n n+1 n+2 n n+1 n+2 n n+1 n+2 n+3 n+4 n+5 vro31 aaa y e7 y e7 y e7 r7 r7 r7 y a7 y a7 y a7 vro30 r4 r4 r4 y e6 y e6 y e6 r6 r6 r6 y a6 y a6 y a6 vro29 r3 r3 r3 y e5 y e5 y e5 r5 r5 r5 y a5 y a5 y a5 vro28 r2 r2 r2 y e4 y e4 y e4 r4 r4 r4 y a4 y a4 y a4 vro27 r1 r1 r1 y e3 y e3 y e3 r3 r3 r3 y a3 y a3 y a3 vro26 r0 r0 r0 y e2 y e2 y e2 r2 r2 r2 y a2 y a2 y a2 vro25 g4 g4 g4 y e1 y e1 y e1 r1 r1 r1 y a1 y a1 y a1 vro24 g3 g3 g3 y e0 y e0 y e0 r0 r0 r0 y a0 y a0 y a0 vro23 g2 g2 g2 u e7 u e7 u e7 g7 g7 g7 y b7 y b7 y b7 vro22 g1 g1 g1 u e6 u e6 u e6 g6 g6 g6 y b6 y b6 y b6 vro21 g0 g0 g0 u e5 u e5 u e5 g5 g5 g5 y b5 y b5 y b5 vro20 b4 b4 b4 u e4 u e4 u e4 g4 g4 g4 y b4 y b4 y b4 vro19 b3 b3 b3 u e3 u e3 u e3 g3 g3 g3 y b3 y b3 y b3 vro18 b2 b2 b2 u e2 u e2 u e2 g2 g2 g2 y b2 y b2 y b2 vro17 b1 b1 b1 u e1 u e1 u e1 g1 g1 g1 y b1 y b1 y b1 vro16 b0 b0 b0 u e0 u e0 u e0 g0 g0 g0 y b0 y b0 y b0
1996 sep 04 39 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 7 vram port output data formats (vro15 to vro0) at fs2 bit = 1 and vof bit = 1 (can be set via i 2 c-bus), burst and transparent mode, pixel order = n, n + 1, n + 2, etc. notes 1. a = keying bit. 2. rgb = digital signals. pixel output bits fs1 = 0; fs0 = 0 rgb (5 , 5 , 5) + a 16-bit words (1)(2) fs1 = 0; fs0 = 1 yuv4:2:2 16-bit words (1)(2) fs1 = 1; fs0 = 0 rgb (8 , 8 , 8) 24-bit words (1)(2) fs1 = 1; fs0 = 1 8-bit monochrome 16-bit words (1) n n+1 n+2 n n+1 n+2 n n+1 n+2 n n+1 n+2 n+3 n+4 n+5 vro15 x x xxxxb7b7b7xxx vro140 x x xxxxb6b6b6xxx vro13 x x xxxxb5b5b5xxx vro12 x x xxxxb4b4b4xxx vro11 x x xxxxb3b3b3xxx vro10 x x xxxxb2b2b2xxx vro9 x x xxxxb1b1b1xxx vro8 x x xxxxb0b0b0xxx vro7 a aaaaaaaaaaa vro6 ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) vro5 ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) vro4 ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) vro3 ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) vro2 ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) vro1 ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) vro0 ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a) ( a)
1996 sep 04 40 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 8 optional vram port output data formats (vro31 to vro16) at fs2 bit = 0 and vof bit = 0 (can be set via i 2 c-bus), burst mode only; pixel order = n, n + 1, n + 2, etc.; vmux = 1 or 0 notes 1. a = keying bit. 2. rgb and yuv = digital signals. 3. z = high ohmic (3-state). 4. e = even pixel numbers. 5. a and b = consecutive pixels. pixel output bits fs1 = 0, fs0 = 0 rgb (5 , 5 , 5) + a 32-bit long word (1)(2)(3) fs1 = 0, fs0 = 1 yuv 4 :2:2 32-bit long word (2)(4) fs1 = 1, fs0 = 1 8-bit monochrome 32-bit long word (5) n n+2 n n+2 n n+1 n+4 n+5 101010101010 vro31 a z a zy e7 zy e7 zy a7 zy a7 z vro30 r4 z r4 z y e6 zy e6 zy a6 zy a6 z vro29 r3 z r3 z y e5 zy e5 zy a5 zy a5 z vro28 r2 z r2 z y e4 zy e4 zy a4 zy a4 z vro27 r1 z r1 z y e3 zy e3 zy a3 zy a3 z vro26 r0 z r0 z y e2 zy e2 zy a2 zy a2 z vro25 g4 z g4 z y e1 zy e1 zy a1 zy a1 z vro24 g3 z g3 z y e0 zy e0 zy a0 zy a0 z vro23 g2 z g2 z u e7 zu e7 zy b7 zy b7 z vro22 g1 z g1 z u e6 zu e6 zy b6 zy b6 z vro21 g0 z g0 z u e5 zu e5 zy b5 zy b5 z vro20 b4 z b4 z u e4 zu e4 zy b4 zy b4 z vro19 b3 z b3 z u e3 zu e3 zy b3 zy b3 z vro18 b2 z b2 z u e2 zu e2 zy b2 zy b2 z vro17 b1 z b1 z u e1 zu e1 zy b1 zy b1 z vro16 b0 z b0 z u e0 zu e0 zy b0 zy b0 z
1996 sep 04 41 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 9 optional vram port output data formats (vro15 to vro0) at fs2 bit = 0 and vof bit = 0 (can be set via i 2 c-bus), burst mode only; pixel order = n, n + 1, n + 2, etc.; vmux = 1 or 0 notes 1. a = keying bit. 2. rgb and yuv = digital signals. 3. z = high ohmic (3-state). 4. o = odd pixel numbers. 5. e = even pixel number. 6. c and d = consecutive pixels. pixel output bits fs1 = 0, fs0 = 0 rgb (5 , 5 , 5) + a 32-bit long word (1)(2)(3) fs1 = 0, fs0 = 1 yuv 4 :2:2 32-bit long word (2)(3)(4)(5) fs1 = 1, fs0 = 1 8-bit monochrome 32-bit long word (3)(6) n+1 n+3 n+1 n+3 n+2 n+3 n+6 n+7 101010101010 vro15 z a z a zy o7 zy o7 zy c7 zy c7 vro14 z r4 z r4 z y o6 zy o6 zy c6 zy c6 vro13 z r3 z r3 z y o5 zy o5 zy c5 zy c5 vro12 z r2 z r2 z y o4 zy o4 zy c4 zy c4 vro11 z r1 z r1 z y o3 zy o3 zy c3 zy c3 vro10 z r0 z r0 z y o2 zy o2 zy c2 zy c2 vro9 z g4 z g4 z y o1 zy o1 zy c1 zy c1 vro8 z g3 z g3 z y o0 zy o0 zy c0 zy c0 vro7 z g2 z g2 z v e7 zv e7 zy d7 zy d7 vro6 z g1 z g1 z v e6 zv e6 zy d6 zy d6 vro5 z g0 z g0 z v e5 zv e5 zy d5 zy d5 vro4 z b4 z b4 z v e4 zv e4 zy d4 zy d4 vro3 z b3 z b3 z v e3 zv e3 zy d3 zy d3 vro2 z b2 z b2 z v e2 zv e2 zy d2 zy d2 vro1 z b1 z b1 z v e1 zv e1 zy d1 zy d1 vro0 z b0 z b0 z v e0 zv e0 zy d0 zy d0
1996 sep 04 42 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 8i 2 c-bus protocol 8.1 i 2 c-bus format table 10 i 2 c-bus format table 11 description of i 2 c-bus format table 12 i 2 c-bus status byte (x in address byte = 1; 71h at iicsa = low or 73h at iicsa = high) table 13 function of status bits id3 to id0 (software model of SAA7140A and saa7140b compatible) remark: with the exception of subaddress 20h (read only) all i 2 c-bus registers are read/write registers. s slave address ack subaddress ack data0 ack x datan ack p code description s start condition slave address 0111 00x = iicsa = low or 0111 001x = iicsa = high ack acknowledge generated by the slave subaddress subaddress byte (if more than 1 data byte is transmitted then an auto-increment of the subaddress is performed) data data byte p stop condition x read/write control bit: x = 0, order to write (the circuit is slave receiver) x = 1, order to read (the circuit is slave transmitter) function data bits d7 d6 d5 d4 d3 d2 d1 d0 status byte (subaddress 20h) id3 id2 id1 id0 x x x x id3 id2 id1 id0 version 0 0 0 0 v0 (?rst version)
1996 sep 04 43 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 8.2 i 2 c-bus bitmap table 14 i 2 c-bus decoder control; subaddress and data bytes for writing (x in address byte = 0; 70h at iicsa = low or 72h at iicsa = high); programming set a: subaddress = 02h to 1fh function subaddress data bits d7 d6 d5 d4 d3 d2 d1 d0 df (1) initial settings expansion/dmsd 00 fsel rsen (4) sregs iregs invoe revfld fico1 fico0 initial settings vram 01 vpe ttr (4) vof qpp of1 of0 lw1 lw0 expansion port output control 02 fldc vidc vd1 vd0 hd1 hd0 pxqd llcd expansion i/o control; scaler source control 03 vsyp (4) srio (4) rehaw revaw vsi hsi vipsi llcs expansion/vram format control 04 shvs yuv8 mct rtb dit fs2 fs1 fs0 luminance brightness 05 brig7 brig6 brig5 brig4 brig3 brig2 brig1 brig0 luminance contrast 06 x cont6 cont5 cont4 cont3 cont2 cont1 cont0 chroma saturation 07 x satn6 satn5 satn4 satn3 satn2 satn1 satn0 horizontal window start (2) 08 xo7 xo6 xo5 xo4 xo3 xo2 xo1 xo0 horizontal window length (2) 09 xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 (continue) 0a x xo10 xo9 xo8 x xs10 xs9 xs8 horizontal phase offset 0b xp7 xp6 xp5 xp4 xp3 xp2 xp1 xp0 vertical window start (3) 0c yo7 yo6 yo5 yo4 yo3 yo2 yo1 yo0 vertical window length (3) 0d ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 (continue) 0e x yo10 yo9 yo8 x ys10 ys9 ys8 vertical phase offset 0f x yp6 (4) yp5 yp4 yp3 yp2 yp1 yp0 horizontal prescaling 10 x xacm (4) xpsc5 xpsc4 xpsc3 xpsc2 xpsc1 xpsc0 horizontal weighting control (select y) 11 cxy7 cxy6 cxy5 cxy4 cxy3 cxy2 cxy1 cxy0 horizontal weighting control (select uv) 12 cxuv7 cxuv6 cxuv5 cxuv4 cxuv3 cxuv2 cxuv1 cxuv0 pre?lter yuv 13 pfuv3 pfuv2 pfuv1 pfuv0 pfy3 pfy2 pfy1 pfy0 vertical interpolation control 14 flip yacm yacl5 yacl4 yacl3 yacl2 yacl1 yacl0 vertical weighting control 1 15 cya7 cya6 cya5 cya4 cya3 cya2 cya1 cya0 vertical weighting control 2 16 cyb7 cyb6 cyb5 cyb4 cyb3 cyb2 cyb1 cyb0 dc gain normalization 17 x dcgx2 dcgx1 dcgx0 x dcgy2 dcgy1 dcgy0 horizontal scaling increment 18 xsci7 xsci6 xsci5 xsci4 xsci3 xsci2 xsci1 xsci0 (continue) 19 x x x x xsci11 xsci10 xsci9 xsci8 vertical scaling increment 1a ysci7 ysci6 ysci5 ysci4 ysci3 ysci2 ysci1 ysci0 (continue) 1b x x x x x x ysci9 ysci8
1996 sep 04 44 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b chroma keying upper limit for v 1c vu7 vu6 vu5 vu4 vu3 vu2 vu1 vu0 chroma keying lower limit for v 1d vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 chroma keying upper limit for u 1e uu7 uu6 uu5 uu4 uu3 uu2 uu1 uu0 chroma keying lower limit for u 1f ul7 ul6 ul5 ul4 ul3 ul2 ul1 ul0 programming set b; subaddress = 22h to 3fh read only register 20 id3 id2 id1 id0 x x x x i/o port enable 21 pen3 (4) pen2 (4) pen1 (4) pen0 (4) port3 port2 port1 port0 expansion port output control 22 fldc vidc vd1 vd0 hd1 hd0 pxqd llcd expansion i/o control; scaler source control 23 vsyp (4) srio (4) rehaw revaw vsi hsi vipsi llcs expansion/vram format control 24 shvs yuv8 mct rtb dit fs2 fs1 fs0 luminance brightness 25 brig7 brig6 brig5 brig4 brig3 brig2 brig1 brig0 luminance contrast 26 x cont6 cont5 cont4 cont3 cont2 cont1 cont0 chroma saturation 27 x satn6 satn5 satn4 satn3 satn2 satn1 satn0 horizontal window start (5) 28 xo7 xo6 xo5 xo4 xo3 xo2 xo1 xo0 horizontal window length (5) 29 xs7 xs6 xs5 xs4 xs3 xs2 xs1 xs0 (continue) 2a x xo10 xo9 xo8 x xs10 xs9 xs8 horizontal phase offset 2b xp7 xp6 xp5 xp4 xp3 xp2 xp1 xp0 vertical window start (6) 2c yo7 yo6 yo5 yo4 yo3 yo2 yo1 yo0 vertical window length (6) 2d ys7 ys6 ys5 ys4 ys3 ys2 ys1 ys0 (continue) 2e x yo10 yo9 yo8 x ys10 ys9 ys8 vertical phase offset 2f ypf yp6 (4) yp5 yp4 yp3 yp2 yp1 yp0 horizontal prescaling 30 x xacm (4) xpsc5 xpsc4 xpsc3 xpsc2 xpsc1 xpsc0 horizontal weighting control (select y) 31 cxy7 cxy6 cxy5 cxy4 cxy3 cxy2 cxy1 cxy0 horizontal weighting control (select uv) 32 cxuv7 cxuv6 cxuv5 cxuv4 cxuv3 cxuv2 cxuv1 cxuv0 pre?lter yuv 33 pfuv3 pfuv2 pfuv1 pfuv0 pfy3 pfy2 pfy1 pfy0 vertical interpolation control 34 flip yacm yacl5 yacl4 yacl3 yacl2 yacl1 yacl0 vertical weighting control 1 35 cya7 cya6 cya5 cya4 cya3 cya2 cya1 cya0 vertical weighting control 2 36 cyb7 cyb6 cyb5 cyb4 cyb3 cyb2 cyb1 cyb0 dc gain normalization 37 x dcgx2 dcgx1 dcgx0 x dcgy2 dcgy1 dcgy0 horizontal scaling increment 38 xsci7 xsci6 xsci5 xsci4 xsci3 xsci2 xsci1 xsci0 function subaddress data bits d7 d6 d5 d4 d3 d2 d1 d0 df (1)
1996 sep 04 45 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b notes 1. default register contents to be filled in by hand. 2. continued in 0a. 3. continued in 0e. 4. bits set to logic 1 after reset (all other bits set to logic 0 after reset). 5. continued in 2a. 6. continued in 2e. (continue) 39 x x x x xsci11 xsci10 xsci9 xsci8 vertical scaling increment 3a ysci7 ysci6 ysci5 ysci4 ysci3 ysci2 ysci1 ysci0 (continue) 3b x x x x x x ysci9 ysci8 chroma keying upper limit for v 3c vu7 vu6 vu5 vu4 vu3 vu2 vu1 vu0 chroma keying lower limit for v 3d vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 chroma keying upper limit for u 3e uu7 uu6 uu5 uu4 uu3 uu2 uu1 uu0 chroma keying lower limit for u 3f ul7 ul6 ul5 ul4 ul3 ul2 ul1 ul0 function subaddress data bits d7 d6 d5 d4 d3 d2 d1 d0 df (1)
1996 sep 04 46 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 8.3 description of the i 2 c-bus bits tables 15 to 21 give the function of the register bits given in table 14. 8.3.1 i nitial settings for the expansion and dmsd port ; subaddress 00h table 15 field detection; data bits fico1 to fico0 table 16 reference edge selection for the v sync input of the ?eld detection; data bit revfld table 17 polarity selection for the h sync input of the ?eld detection (note 1); data bit invoe note 1. invoe may also be used for fdio and fldv output signal inversion table 18 polarity of i 2 c-bus register set id; data bit iregs table 19 fix i 2 c-bus register set id; data bit sregs table 20 enable of reference signals pxqio, hio, vio, fdio, llcio (expansion port) and pxqv, hgtv, vsyv, fldv (vram port); data bit rsen fico1 fico0 description 0 0 ?eld sequence as detected from h and v sync signals 0 1 ?eld sequence synchronized to h and v but noise limited 1 0 free running ?eld sequence 1 1 reserved revfld description 0 rising edge is reference 1 falling edge is reference invoe description 0 active low, e.g. for saa71xx signals similar to href 1 active high, e.g. for saa71xx signals similar to hs iregs description 0 register set id as de?ned by sregs 1 register set id inverted sregs description 0 register set id toggles as detected and de?ned by fico0 and fico1 1 register set id ?xed to 1 (register set b selected) rsen description 0 reference signals enabled 1 reference signals disabled
1996 sep 04 47 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 21 field sync de?nition; data bit fsel 8.3.2 i nitial settings for the vram port ; subaddress 01h table 22 first pixel position in vro data for fs1 = 0; fs0 = 0 (rgb) and fs1 = 0; fs0 = 1 (yuv); data bits lw1 and lw0 table 23 first pixel position in vro data for fs1 = 1; fs0 = 1 (monochrome) table 24 set output ?eld mode; data bits of1 to of0 table 25 pixel quali?er polarity ?ag; data bit qpp table 26 vram-port output format; data bit vof fsel description 0 v input for ?eld detection to be handled as v sync signal 1 v input for ?eld detection to be handled as frame sync signal lw1 lw0 bits 31 to 24 bits 23 to 16 bits 15 to 8 bits 7 to 0 remark 0 0 pixel 0 pixel 0 pixel 1 pixel 1 fs2 = 0; ttr = 0 0 1 pixel 0 pixel 0 pixel 1 pixel 1 1 0 black black pixel 0 pixel 0 1 1 black black pixel 0 pixel 0 lw1 lw0 bits 31 to 24 bits 23 to 16 bits 15 to 8 bits 7 to 0 remark 0 0 pixel 0 pixel 1 pixel 2 pixel 3 fs2 = 0; ttr = 0 0 1 black pixel 0 pixel 1 pixel 2 1 0 black black pixel 0 pixel 1 1 1 black black black pixel 0 0 0 pixel 0 pixel 1 x x fs2 = 1; ttr = 0; lw only affects the grey scale format 0 1 black pixel 0 x x 1 0 pixel 0 pixel 1 x x 1 1 black pixel 0 x x of1 of0 description 0 0 both ?elds for interlaced storage 0 1 both ?elds for non-interlaced storage 1 0 odd ?elds only (even ?elds ignored) for non-interlaced storage 1 1 even ?elds only (odd ?elds ignored) for non-interlaced storage qpp description 0 pxqv is active low (pin 41) 1 pxqv is active high vof description 0 enabling of 32 to 16-bit multiplexing via vmux 1 disabling of 32 to 16-bit multiplexing via vmux
1996 sep 04 48 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 27 vram-port mode selection; data bit ttr table 28 vram-port outputs enable; data bit vpe 8.3.3 p ort i/o control ; subaddress 21h table 29 select direction of port3 to port0; data bits pen3 to pen0 table 30 status of port i/os, pins 32 (port3) to 35 (port0) 8.3.4 r egister set a (02h to 1fh) and b (22h to 3fh) table 31 source select for expansion port clock output llcio (note 1 ); data bit llcd note 1. the clock output on llcio may be disabled by i 2 c-bus bits srio = 1 and llcs = 1; see table 37. table 32 source select for expansion port pixel quali?er and data output at pxqio and vidh/vidl[7 to 0] (note 1); data bit pxqd note 1. the qualifier output on pxqio may be disabled by i 2 c-bus bits srio = 1 and vipsi = 1; see table 38. ttr description 0 fifo mode (vram data burst transfer) 1 transparent mode vpe description 0 hfl and incadr inactive (hfl = low, incadr = high); vro outputs in 3-state 1 hfl and incadr enabled; vro outputs dependent on voen pen3 to pen0 description penx = 0 portx set to output penx = 1 portx set to input port3 to port0 description write mode set status of port3 to port0 registers (applied to pins 32 to 35 if penx = 0) read mode read status of port3 to port0; if penx = 0 then status of portx register; if penx = 1 then status of external driven data llcd description 0 source is clock from dmsd port 1 source is clock input from expansion port, as de?ned by srio pxqd description 0 sources are corresponding signals from dmsd port 1 sources are corresponding signals from scaler output
1996 sep 04 49 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 33 source select for expansion port horizontal sync output hio (note 1); data bits hd1 to hd0 note 1. if srio and hsi = 1 then hio output is disabled. table 34 source select for expansion port vertical sync output vio (note 1); data bits vd1 to vd0 note 1. if srio and vsi = 1 then vio output is disabled. table 35 i/o control for the expansion port data output vidh7 to vidh0 and vidl7 to vidl0 (dependent on yuv8 programming for fldc = 0) (note 1); data bit vidc note 1. if fldc and fdio) = 1 the outputs vidh/vidl are disabled. table 36 fdio i/o control and signal de?nition; data bit fldc hd1 hd0 description 0 0 source is corresponding signal from dmsd port 0 1 source is hin from expansion port (short-cut) 1 0 source is corresponding signal from scaler output 1 1 source is hin from expansion port vd1 vd0 description 0 0 source is corresponding signal from dmsd port 0 1 source is vin from expansion port (short-cut) 1 0 source is corresponding signal from scaler output 1 1 source is vin from expansion port yuv8 vidc description 0 0 vidh = output, vidl = output 0 1 vidh = input, vidl = input 1 0 vidh = output, vidl = input 1 1 vidh = input, vidl = output fldc fdio description 0 - fdio contains odd/even ?ag fld and is switched to output 1 - fdio may be provided with a 7196 dir like signal and is switched to input - 0 llcio, pxqio and vidh/vidl i/o de?nition as de?ned by the i 2 c-bus parameters - 1 selected outputs are forced to input mode and corresponding signals are used as scaler input
1996 sep 04 50 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 37 source select for scaler clock input; data bit llcs (03h to 23h) table 38 source select for scaler data and pixel quali?er input; data bit vipsi table 39 source select for scaler horizontal sync input; data bit hsi table 40 source select for scaler vertical sync input and ?eld detection h/v; data bit vsi table 41 reference edge selection for the v sync input of the acquisition window; data bit revaw fldc fdio srio llcs description x x x 0 source is llc from dmsd port x x 0 1 source is llcin from expansion port 0 x 1 1 source is llcio input from expansion port, output is disabled 1 0 1 1 source is derived from llcio output; llcd = 0 from llc of decoder port, llcd = 1 not allowed 1 1 1 1 source is llcio input from expansion port, output is disabled fldc fdio srio vipsi description 0 x x 0 source is data and cref from dmsd port 0x - 1 source is data input vidh/vidl: when the pixel quali?er is pxqin from expansion port fldc = 0, fdio = x, srio = 0 and vipsi = 1; when the pixel quali?er is pxqio from expansion port, output disabled fldc = 0, fdio = x, srio = 1 and vipsi = 1; 10 - x source is derived from data output vidh/vidl, from decoder port for pxqd = 0, pxqd = 1 is not allowed: when the pixel quali?er is pxqin from expansion port fldc = 1, fdio = 0, srio = 0 and vipsi = x; when the pixel quali?er is cref via the pxqio output for pxqd = 0, pxqd = 1 is not allowed fldc = 1, fdio = 0, srio = 1 and vipsi = x 11 - x source is data input vidh/vidl, output disabled, when the pixel quali?er is pxqin from expansion port fldc = 1, fdio = 1, srio = 0 and vipsi = x; when the pixel quali?er is pxqio from expansion, port output disabled fldc = 1, fdio = 1, srio = 1 and vipsi = x srio hsi description x 0 source is href from dmsd port 0 1 source is hin from expansion port 1 1 source is hio from expansion port, hio output disabled srio vsi description x 0 source is vs from dmsd port; vs and href for ?eld detection 0 1 source is vin from expansion port; vin and hin for ?eld detection 1 1 source is vio from expansion port; vio and hio for ?eld detection revaw description 0 rising edge is reference 1 falling edge is reference
1996 sep 04 51 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 42 reference edge selection for the h-sync input of the acquisition window; data bit rehaw table 43 expansion-port clock and reference signal selection; data bit srio (see tables 37 to 40) table 44 vsyv output signal polarity; data bit vsyp table 45 vram port output format select; data bits fs2 to fs0 (04h to 24h); see tables 6 and 7 table 46 dithering (noise shaping) control (for vram port only); data bit dit table 47 rom table for anti-gamma correction (for vram port only); data bit rtb rehaw description 0 rising edge is reference 1 falling edge is reference srio description 0 clock and reference signals are taken from xxxin pins 1 clock and reference signals are taken from xxxio pin, xxxin pins are ignored vsyp description 0 vsyv contains 1 active v sync signals 1 vsyv contains 0 active v sync signals fs2 fs1 fs0 output format 0 0 0 rgb (5, 5, 5) + a ; 2 16-bit/pixel; 32-bit word length; rgb matrix on, vram output format 0 0 1 yuv 4:2:2; 2 16-bit/pixel; 32-bit word length; rgb matrix off, vram output format 0 1 0 yuv 4 : 2 : 2; 1 16-bit/pixel; 16-bit word length; rgb matrix off, optional output format 0 1 1 monochrome mode; 4 8-bit/pixel; 32-bit word length; rgb matrix off, vram output format 1 0 0 rgb (5, 5, 5) + a ; 1 16-bit/pixel; 16-bit word length; rgb matrix on, vram output + transparent format 1 0 1 yuv 4:2:2+ a ; 1 16-bit/pixel; 16-bit word length; rgb matrix off; vram output + transparent format 1 1 0 rgb (8, 8, 8) + a ; 1 24-bit/pixel; 24-bit word length; rgb matrix on, vram output + transparent format 1 1 1 monochrome mode; 2 8-bit/pixel; 16-bit word length; rgb matrix off, vram output + transparent format dit description 0 dithering on 1 dithering off rtb description 0 rom table switched on 1 rom table switched off
1996 sep 04 52 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 48 monochrome and twos complement output data select; data bit mct table 49 expansion port data path con?guration; data bit yuv8; see tables 8 and 9 table 50 select ?eld sequence, h and v; data bit shvs table 51 luminance brightness control; data bits brig7 to brig0 (05h to 25h) table 52 luminance contrast control; data bits cont6 to cont0 (06h to 26h) table 53 chrominance saturation control; data bits satn6 to satn0 (07h to 27h) mct description 0 inverse grey scale luminance (if grey scale is selected by fs bits) or straight binary u, v data output 1 non-inverse monochrome luminance (if grey scale is selected by fs bits) or twos complement u, v data output yuv8 description 0 expansion port set to 16-bit yuv 1 expansion port set to 8-bit yuv (vidl7 to vidl0) shvs description 0 use separate h and v input signals 1 use decoded information from the ccir 656 data stream (only for yuv8 = 1) d7 d6 d5 d4 d3 d2 d1 d0 gain 1 1 1 1 1 1 1 1 255 (bright) ... ... ... ... ... ... ... ... .... 1 0 0 0 0 0 0 0 128 (ccir level) ... ... ... ... ... ... ... ... .... 0 0 0 0 0 0 0 0 0 (dark) d7 d6 d5 d4 d3 d2 d1 d0 gain 0 1 1 1 1 1 1 1 1.999 (maximum contrast) ... ... ... ... ... ... ... ... .... 0 1 0 0 0 0 0 0 1 (ccir level) ... ... ... ... ... ... ... ... .... 0 0 0 0 0 0 0 0 0 (luminance off) d7 d6 d5 d4 d3 d2 d1 d0 gain 0 1 1 1 1 1 1 1 1.999 (maximum contrast) ... ... ... ... ... ... ... ... .... 0 1 0 0 0 0 0 0 1 (ccir level) ... ... ... ... ... ... ... ... .... 0 0 0 0 0 0 0 0 0 (colour off)
1996 sep 04 53 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 54 x (horizontal) offset de?nition, counted in input pixel quali?ers; data bits xo10 to xo0 table 55 x (horizontal) source size de?nition, counted in input pixel quali?ers; data bits xs10 to xs0 table 56 start phase for horizontal variable phase scaling (de?ned by xsci11 to xsci0); data bits xp6 to xp0 table 57 x phase value ?xed; data bit xp7 table 58 y (vertical) offset de?nition, counted in input horizontal sync events; yo10 to yo0 table 59 y (vertical) source size de?nition, counted in input horizontal sync events; ys10 to ys0 table 60 start phase for vertical scaling (de?ned by ysci9 to ysci0); data bits yp6 to yp0 table 61 prescaling factor of the x prescaler; data bits xpsc5 to xpsc0 xo10 to xo0 description 08h to 28h and 0ah to 2ah de?nes the start position of the x processing window xs10 to xs0 description 09h to 29h and 0ah to 2ah de?nes the length of the x processing window xp6 to xp0 description 0bh to 2bh xp start = xp/128 t pxq (t pxq = distance between 2 pixels) xp7 description 0 sample phase is calculated for every quali?ed sample 1 sample phase is ?xed to the value set by xp6 to xp0 yo10 to yo0 description 0ch to 2ch and 0eh to 2eh de?nes the start position of the y processing window ys10 to ys0 description 0dh to 2dh and 0eh to 2eh de?nes the length of the y processing window yp6 to yp0 description 0fh to 2fh yp start = yp/128 t line (t line = distance between 2 lines) xpsc5 to xpsc0 description 10h to 30h de?nes accumulation sequence length and subsampling factor of the input data stream where n op (xpsc) = trunc [n in M (xpsc + 1)] n op = number of prescaler output pixel and n in = number of quali?ed scaler input pixel
1996 sep 04 54 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 62 x (horizontal) prescaler accumulation mode of accumulating fir; data bit xacm table 63 coef?cient select for x prescaler (luminance component y); data bits cxy7 to cxy0 table 64 coef?cient select for x prescaler (colour difference signals uv); data bits cxuv7 to cxuv0 table 65 pre?lter selection for luminance component y (note 1); data bits pfy3 to pfy0 (13h to 33h) note 1. h(z) = h1(z) h2(z) h3(z) with h1 and h 3=1+z - 1 ; h2 = 1 + a z - 1 +z - 2 and a = 2, 15 16 , 7 8 , 3 4 for pfy3 and pfy2 = 00, 01, 10, 11. table 66 pre?lter selection for colour difference signals uv (note 1); data bits pfuv3 to pfuv0 note 1. h(z) = h1(z) h2(z) h3(z) with h1 = 1 + z - 1 ; h2 = 1 + a z - 1 +z - 2 ; h3 = 1 + z - 2 and a = 2, 15 16 , 7 8 , 3 4 for pfuv3 and pfuv2 = 00, 01, 10, 11. table 67 accumulation sequence length of the y (vertical) processing; data bits yacl5 to yacl0 xacm description 0 accumulating operates overlapping 1 non overlapping accumulation (must be set to bypass the prescaler) cxy7 to cxy0 description 11h to 31h for dc gain compensation of prescaler the accumulated pixels can be weighted by 1 or 2. cxyi de?nes a sequence of 8 bits, which control the coef?cients; when cxyi = 0 pixel weighted by 1 and when cxyi = 1 pixel weighted by 2 cxuv7 to cxuv0 description 12h to 32h for dc gain compensation of prescaler the accumulated pixels can be weighted by 1 or 2. cxuvi de?nes a sequence of 8 bits, which control the coef?cients; when cxuvi = 0 pixel weighted by 1 and when cxuvi = 1 pixel weighted by 2 pfy1 pfy0 3 h1(z) h2(z) h3(z) 0 0 bypass bypass bypass 0 1 active bypass bypass 1 0 active bypass active 1 1 active active active pfuv1 pfuv0 3 h1(z) h2(z) h3(z) 0 0 bypass bypass bypass 0 1 active bypass bypass 1 0 active active bypass 1 1 active active active yacl5 to yacl0 description 14h to 34h de?nes vertical accumulation sequence length of input lines. if accumulation fir ?lter mode is selected (yacm), yacl has to ?t to the vertical scaling factor (de?ned by ysci9 to ysci0)
1996 sep 04 55 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 68 y (vertical) scaler accumulation (respectively calculation) mode of vertical arithmetic; data bit yacm table 69 horizontal ?ip mirroring; maximum pixels after prescaling = 384; data bit flip table 70 coef?cient select for y (vertical) processing in accumulation mode (notes 1 and 2); data bits cya7 to cya0 and cyb7 to cyb0 (15h to 35h and 16h to 36h) notes 1. for improvement of vertical filtering the accumulated lines can be weighted. weighting factor = 2 (2 cybi + cyai - 1) 2. the resulting factor as a function of a bit pattern cyai, cybi and the dc gain control dcgy, is given in tables 71 and 72. table 71 dc gain control of vertical scaler (see table 2) (notes 1, 2 and 3) ; data bits dcgy2 to dcgy0 (17h to 37h) notes 1. dependent on active coefficients and the sequence length, the amplitude gain has to be renormalized. 2. gain factor = 2 (dcgy + 1) . 3. the resulting factor is a function of cyi and dcgy; 0 for (cyai = cybi = 0) or (cyai = cybi = 1 and dcgy = 0) or (dgcy > 5). the weighting/gain factor is given in table 72. table 72 weighting factor as a function of gain factor yacm description 0 arithmetic operates as a linear phase interpolator (lpi) 1 arithmetic operates as accumulating fir ?lter in vertical direction flip description 0 output lines correspond to input lines 1 output lines correspond ?ipped input lines (see section 7.4.2) cybi cyai cyi weighting factor 0000 0111 1022 1134 dcgy2 dcgy1 dcgy0 dcgy gain factor 00002 00114 ... .... .... .... .... ... .... .... .... .... 1117256 cyi dcgy0 dcgy1 dcgy2 dcgy3 dcgy4 dcgy5 dcgy6 dcgy7 000000000 1 1 2 1 4 1 8 1 16 1 32 1 64 00 21 1 2 1 4 1 8 1 16 1 32 00 301 1 2 1 4 1 8 1 16 00
1996 sep 04 56 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 73 dc gain control of horizontal prescaler (see table 1; note 1); data bits dcgx2 to dcgx0 note 1. dependent on the number of active coefficients 2 in the accumulation sequence and the sequence length, the output amplitude gain has to be renormalization via dcgx. table 74 x scaler increment for variable phase scaling in horizontal pixel phase arithmetic (note 1); data bits xsci11 to xsci0 (18h to 38h and 19h to 39h) note 1. where n ip = number of qualified scaler input pixel and n op = number of output pixel. table 75 y scaler increment for vertical down scaling; data bits ysci9 to ysci0 (1ah to 3ah and 1bh to 3bh) table 76 set upper limit v for colour keying (8-bit; twos complement); data bits vu7 to vu0 (1ch to 3ch) table 77 set lower limit v for colour keying (8-bit; twos complement); data bits vl7 to vl0 (1dh to 3dh) dcgx2 dcgx1 dcgx0 gain 000 1 001 1 2 010 1 4 011 1 8 100 1 2 101 1 4 110 1 8 111 1 16 xsci11 to xsci0 description 18h to 38h and 19h to 39h ysci9 to ysci0 description 1ah to 3ah ; for yacm = 0 = lpi mode 1bh to 3bh ; for yacm = 1 = accumulation mode vu7 vu6 vu5 vu4 vu3 vu2 vu1 vu0 description 10000000as maximum negative value = - 128 signal level 00000000 limit = 0 01111111as maximum positive value = +127 signal level vl7 vl6 vl5 vl4 vl3 vl2 vl1 vl0 description 10000000as maximum negative value = - 128 signal level 00000000 limit = 0 01111111as maximum positive value = +127 signal level xsci int n ip n op ---------- - 1024 xpsc 1 + () --------------------------------- - = ysci int 1024 n il n ol ---------- 1 C ? ? ?? = ysci int 1024 1 n ol n il ---------- C ? ? ?? =
1996 sep 04 57 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b table 78 set upper limit u for colour keying (8-bit; twos complement); data bits uu7 to uu0 (1eh to 3eh) table 79 set lower limit u for colour keying (8-bit; twos complement); data bits ul7 to ul0 (1fh to 3fh) 9 limiting values in accordance with the absolute maximum rating system (iec 134). note 1. pin 31 (sda): 800 v. 10 handling inputs and output are protected against electrostatic discharge in normal handling. however, to be totally safe, it is desirable to take normal precautions appropriate to handling mos devices. 11 thermal characteristics uu7 uu6 uu5 uu4 uu3 uu2 uu1 uu0 description 10000000as maximum negative value = - 128 signal level 00000000 limit = 0 01111111as maximum positive value = +127 signal level ul7 ul6 ul5 ul4 ul3 ul2 ul1 ul0 description 10000000as maximum negative value = - 128 signal level 00000000 limit = 0 01111111as maximum positive value = +127 signal level symbol parameter conditions min. max. unit v ddd(bord) digital supply voltage for i/o section SAA7140A - 0.5 +6.5 v v ddd(core) digital supply voltage for internal core SAA7140A - 0.5 +6.0 v v ddd digital supply voltage saa7140b - 0.5 +6.0 v v i dc input voltage saa7140b - 0.5 v ddd + 0.5 v v o dc output voltage saa7140b - 0.5 v ddd + 0.5 v p tot total power dissipation SAA7140A - 750 mw saa7140b - 750 mw t stg storage temperature - 65 +150 c t amb operating ambient temperature 0 70 c v esd electrostatic protection 2000 (1) - v symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 60 k/w
1996 sep 04 58 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 12 dc characteristics v ddd(bord) = 4.5 to 5.5 v; v ddd(core) = 3.0 to 3.6 v; v ddd = 3.0 to 3.6 v; t amb = 0 to 70 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supplies; SAA7140A v ddd(bord) digital supply voltage for i/o section 4.5 5.0 5.5 v v ddd(core) digital supply voltage for internal core 3.0 3.3 3.6 v i ddd(bord) digital supply current for i/o section normal operation - 30 - ma sleep mode - 10 - ma i ddd(core) digital supply current for internal core normal operation - 60 - ma sleep mode - 10 - ma i ddd(tot) total digital supply current - 100 - ma supplies; saa7140b v ddd digital supply voltage 3.0 3.3 3.6 v i ddd digital supply current normal operation - 90 - ma sleep mode - 10 - ma data, clock and control inputs v il low level input voltage clocks - 0.5 - 0.6 v v ih high level input voltage clocks 2.4 - v ddd + 0.5 v v il low level input voltage other inputs; SAA7140A - 0.5 - 0.8 v other inputs; saa7140b - 0.5 - 0.2v ddd v v ih high level input voltage other inputs; SAA7140A 2.0 - v ddd + 0.5 v other inputs; saa7140b 2.4 - v ddd + 0.5 v i li input leakage current v il =0v -- 1ma c i input capacitance data -- 8pf clocks -- 8pf 3-state i/o; high-impedance state -- 8pf data, clock and control outputs (note 1) v ol low level output voltage all outputs; SAA7140A 0 - 0.6 v clocks; saa7140b 0 - 0.4 v v oh high level output voltage clocks; SAA7140A 2.6 - v ddd v clocks; saa7140b 0.85v ddd - v ddd v v oh high level output voltage other outputs; SAA7140A 2.4 - v ddd v other outputs; saa7140b 0.85v ddd - v ddd v v ol low level output voltage other outputs; saa7140b 0 - 0.4 v
1996 sep 04 59 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b note 1. levels measured with load circuit; 1.2 k w at 3 v (ttl load); c l = 40 pf. 13 ac characteristics v ddd(bord) = 4.5 to 5.5 v; v ddd(core) = 3.0 to 3.6 v; v ddd = 3.0 to 3.6 v; t amb = 0 to 70 c; unless otherwise speci?ed. i 2 c-bus, sda and scl (pins 31 and 32) v il low level input voltage SAA7140A - 0.5 - +1.5 v saa7140b - 0.5 - 0.3v ddd v v ih high level input voltage 0.7v ddd - v ddd + 0.5 v i 31, 32 input current -- 10 m a i ack output current on pin 31 acknowledge 3 -- ma v o output voltage at acknowledge i 31 =3ma -- 0.4 v symbol parameter conditions min. typ. max. unit clock input timing (llc, llcin and llcio as input) (see fig.20) t llc , t llcin cycle time 31 - 45 ns d duty factor t llch or t llc 40 50 60 % t r rise time -- 5ns t f fall time -- 6ns vclk input timing (for burst mode only, ttr = 0); note 1 (see fig.19) t vclk vram port clock cycle time note 2 30 - 200 ns t pl vclk low time note 3 12 -- ns t ph vclk high time note 3 12 -- ns t r rise time 0.6 v to 0.85v ddd -- 5ns t f fall time 0.85v ddd to 0.6 v -- 6ns data and control input timing, related to the corresponding input clock; (see fig.20) t su set-up time 11 -- ns t hd hold time 3 -- ns data and control input timing at the expansion port, related to llcio output t su set-up time 15 -- ns t hd hold time 0 -- ns clock output timing (llcio and vclk output); note 4 (see fig.20) c l output load capacitance 15 - 40 pf t llcio cycle time 31 - 45 ns d duty factor t llcioh or t llcio 38 49 59 % t r rise time 0.6 v to 0.85v ddd -- 5ns t f fall time 0.85v ddd to 0.6 v -- 6ns symbol parameter conditions min. typ. max. unit
1996 sep 04 60 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b notes 1. llc scaler may be llc from dmsd port or llcin from expansion-port, dependent on scaler source clock selection via i 2 c-bus bit llcs. 2. maximum t vclk = 200 ns for test mode only. the applicable maximum cycle time depends on data format, horizontal scaling and input data rate. 3. measured at 1.5 v level; t pl may be infinite. 4. llcio out timing also valid for vclkout in transparent mode; (see fig.20). 5. timings of vro refer to the rising edge of vclk. 6. the timing of incadr and the rising edge of hfl always refers to llc scaler . during a vram transfer, the falling edge of hfl is generated by vclk. during horizontal increment and vertical reset cycles, both edges of hfl always refer to llc scaler. 7. asynchronous signals. its timing refers to the 1.5 v switching point of voen input signal (pin 53). 8. the timing refers to the 1.5 v switching point of vmux signal (pin 46) in 32 to 16-bit multiplexing mode. corresponding pairs of vro outputs are together connected. data and control output timing at the expansion port, related to llcio output; (see fig.20) c l load capacitance 15 - 40 pf t ohd output hold time c l = 7.5 pf 1.5 -- ns c l =15pf --- ns t pd propagation delay from positive edge of llcio output c l =40pf -- 15 ns vro and reference signal output timing, related to vclk output; (see fig.19) c l output load capacitance vro outputs 15 - 40 pf other outputs 7.5 - 25 pf t ohd vro data hold time c l = 10 pf; note 5 0 -- ns t ohl related to lcc scaler (incadr, hfl) c l = 10 pf; notes 6 and 1 0 -- ns t ohv related to vclk (hfl) c l = 10 pf; note 6 0 -- ns t od vro data delay time in burst mode (ttr = 0) c l = 40 pf; note 5 -- 25 ns vro data delay time in transparent mode (ttr = 1) c l = 40 pf; note 5 -- 15 ns t odl related to lcc scaler (incadr,hfl) c l = 25 pf; notes 6 and 7 -- 60 ns t odv related to vclk (hfl) c l = 25 pf; note 6 -- 60 ns t d vro disable time to 3-state c l = 40 pf; note 7 -- 40 ns c l = 25 pf; note 8 -- 24 ns t e vro enable time from 3-state c l = 40 pf; note 7 -- 40 ns c l = 25 pf; note 8 -- 25 ns t hfl voe hfl rising edge to vram port enable no zooming -- 810 ns t hfl vclk hfl rising edge to vclk burst no zooming -- 840 ns symbol parameter conditions min. typ. max. unit
1996 sep 04 61 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b fig.19 data output timing (vram port). handbook, full pagewidth t vclk t f t ch t envro t odvro t odvro t ohvro t od t oh t cl t r data output vram port output hfl vclk not valid voen 2.4 v 1.5 v 0.6 v 2.4 v 0.85v dd 1.5 v 0.6 v 0.4 v 0.85v dd 0.4 v mha125
1996 sep 04 62 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b fig.20 data input/output timing (dmsd port and expansion port). handbook, full pagewidth t r t f t s t h clock input llc, llcin input cref, pxqin (pxqio if used as input) clock output llcio data and control inputs (dmsd/expansion port) data and control outputs expansion port t llc , t llcin t llch , t llcinh t s t f t h t od t oh t llcioh t llciol t r 2.4 v 1.5 v 0.6 v 0.85v dd 1.5 v 0.4 v 2.4 v 0.6 v 2.4 v 0.6 v 0.85v dd 0.4 v not valid mha124
1996 sep 04 63 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 14 package outline unit a 1 a 2 a 3 b p ce (1) eh e ll p qz y w v q references outline version european projection issue date iec jedec eiaj mm 0.15 0.05 1.45 1.35 0.25 0.27 0.17 0.20 0.09 14.1 13.9 0.5 16.15 15.85 0.70 0.58 0.81 0.59 7 0 o o 0.12 0.2 0.1 1.0 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot425-1 96-04-02 d (1) (1) (1) 20.1 19.9 h d 22.15 21.85 e z 0.81 0.59 d 0 5 10 mm scale b p e q e a 1 a l p q detail x l (a ) 3 b c b p e h a 2 d h v m b d z d a z e e v m a x 102 103 y w m w m a max. 1.6 lqfp128: plastic low profile quad flat package; 128 leads; body 14 x 20 x 1.4 mm sot425-1 65 64 38 39 1 128 pin 1 index
1996 sep 04 64 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 15 soldering 15.1 introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). 15.2 re?ow soldering reflow soldering techniques are suitable for all qfp and so packages. the choice of heating method may be influenced by larger plastic qfp packages (44 leads, or more). if infrared or vapour phase heating is used and the large packages are not absolutely dry (less than 0.1% moisture content by weight), vaporization of the small amount of moisture in them can cause cracking of the plastic body. for more information, refer to the drypack chapter in our quality reference manual (order code 9398 510 63011). reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. 15.3 wave soldering 15.3.1 qfp wave soldering is not recommended for qfp packages. this is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. if wave soldering cannot be avoided, the following conditions must be observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. even with these conditions, do not consider wave soldering the following packages: qfp52 (sot379-1), qfp100 (sot317-1), qfp100 (sot317-2), qfp100 (sot382-1) or qfp160 (sot322-1). 15.3.2 so wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. 15.3.3 m ethod (qfp and so) during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 15.4 repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1996 sep 04 65 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b 16 definitions 17 life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. 18 purchase of philips i 2 c components data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation. purchase of philips i 2 c components conveys a license under the philips i 2 c patent to use the components in the i 2 c system provided the system conforms to the i 2 c specification defined by philips. this specification can be ordered using the code 9398 393 40011.
1996 sep 04 66 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b notes
1996 sep 04 67 philips semiconductors objective speci?cation high performance scaler (hps) SAA7140A; saa7140b notes
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